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anilinintel
Beginner
824 Views

DMA controller intel fpga IP not working. Its qsys GUI , its documentation is confusing.

I know about msgdma , prefetcher msgdma and its working cases. but now our requirement is to use simple dma (dma controller core IP) but looks like it is not working as expected.

 

i found a c code for this IP in this forum itself , but it is looping over n over again inside a while loop (line no. 74 and 75) . DMA is not happening at all. even no activity on stp(signal tap analyzer).

its GUI details from qsys system is :

{1.dma enabled

2.len register width is 13

3.maximum burst size: 1024

4.fifo depth: 32

check box is enabled to all byte, word, hword, qword }

#include "io.h" #include <stdio.h> #include <sys/alt_dma.h> #include "system.h"   unsigned int value = 0;   void write_memory(unsigned int base, unsigned int len) { int i; for (i=0; i<len; i++) { IOWR_8DIRECT(base, i, value); // printf("Write: memory base 0x%x, address 0x%x, value %d\n", base, i, value); value++; } }   void read_memory(unsigned int base, unsigned int len) { int i; for (i=0; i<len; i++) { int r = IORD_8DIRECT(base, i); printf(" Read: memory base 0x%x, address 0x%x, value 0x%x\n", base, i, r); } }   static volatile int rx_done = 0; static void done (void* handle, void* data) { rx_done++; }   alt_8 *DMA_mem_to_buf(unsigned int src, int nBytes) { alt_8 dst[nBytes];   void *tx_data = (void *) alt_uncached_malloc(src); void *rx_data = (void *) alt_uncached_malloc(&dst); alt_dma_txchan txchan; alt_dma_rxchan rxchan; int rc;   /* Create the transmit channel */ if ((txchan = alt_dma_txchan_open("/dev/dma")) == NULL) { printf("Failed to open transmit channel\n"); exit (1); }   /* Create the receive channel */ if ((rxchan = alt_dma_rxchan_open("/dev/dma")) == NULL) { printf("Failed to open receive channel\n"); exit (1); }   /* Post the transmit request */ if ((rc = alt_dma_txchan_send(txchan, tx_data, nBytes, NULL, NULL)) < 0) { printf("Failed to post transmit request, reason = %i\n", rc); exit (1); }   /* Post the receive request */ if ((rc = alt_dma_rxchan_prepare(rxchan, rx_data, nBytes, done, NULL)) < 0) { printf("Failed to post read request, reason = %i\n", rc); exit (1); }   /* wait for transfer to complete */ while (!rx_done); printf("Transfer successful!\n");   if (memcmp(tx_data, rx_data, nBytes)) { printf("Verification failed\n"); exit (1); } alt_uncached_free(tx_data); alt_uncached_free(rx_data);   return dst; }   int DMA_mem_to_mem(unsigned int src, unsigned int dst, int nBytes) { void *tx_data = (void *) alt_uncached_malloc(src); void *rx_data = (void *) alt_uncached_malloc(dst); alt_dma_txchan txchan; alt_dma_rxchan rxchan; int rc; printf("entered into fun\n"); /* Create the transmit channel */ if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL) { printf("Failed to open transmit channel\n"); exit (1); }   /* Create the receive channel */ if ((rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL) { printf("Failed to open receive channel\n"); exit (1); } printf("ok\n"); /* Post the transmit request */ if ((rc = alt_dma_txchan_send(txchan, tx_data, nBytes, NULL, NULL)) < 0) { printf("Failed to post transmit request, reason = %i\n", rc); exit (1); }   /* Post the receive request */ if ((rc = alt_dma_rxchan_prepare(rxchan, rx_data, nBytes, done, NULL)) < 0) { printf("Failed to post read request, reason = %i\n", rc); exit (1); } printf("ok ok\n"); /* wait for transfer to complete */ while (!rx_done); // while((ctl[0]&1) == 0) printf("Transfer successful!\n");   if (memcmp(tx_data, rx_data, nBytes)) { printf("Verification failed\n"); exit (1); } alt_uncached_free(tx_data); alt_uncached_free(rx_data); }   int main () { unsigned int* src = 0x00040000; unsigned int* dst = 0x00080000; unsigned int* ctl = 0x00051020; int nBytes = 0x80;   printf("Before DMA\n"); write_memory(src, nBytes); read_memory(src, nBytes);   DMA_mem_to_mem(src, dst, nBytes); // DMA_mem_to_buf(src, nBytes);   printf("After DMA\n"); read_memory(dst, nBytes);   printf("\nExiting...%c", 4); // 4 will terminate the console   return 0; }

please someone come up to resolve this issue. Thanks

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1 Reply
Nathan_R_Intel
Employee
31 Views

Hie, I will need more details as below. In general the DMA controllers offered by Intel FPGA's reference designs have been validate to be functional. Hence, if you are using the correct reference design, it will at least show some activity. I am also not familiar which file you go the above code from. Hence, please check if you can provide the following information for me to assist you: i. FPGA device (Arria 10, Stratix 10 or?) ii. Confirm Interface type used is AVMM-DMA iii. Gen and width iv. Quartus version used v. Where did you get the reference design? Regards, Nathan