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DSP Block Stratix 10 - Multiply Accumulate

Navaneeth
Novice
1,296 Views

Hi

We wish to perform c = c + (a * b) where,

a, b and c are 32-bit unsigned numbers.


Please let us know how best to implement this multiply-accumulate in Verilog so that the DSP blocks available in Stratix 10 can be utilized to achieve the highest Fmax possible.

 

We are okay with either fixed / floating point numbers not necessarily unsigned if that will help achieve higher Fmax (but the data width is 32 bits).

We also don't mind the latency in terms of any number of clock cycles from input to output.

 

Thanks

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1 Solution
Kshitij_Intel
Employee
1,245 Views

Hi,

 

You can also check the full design template within Quartus.

 

Capture.PNG

 

Thank you

Kshitij Goel

 

 

 

View solution in original post

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4 Replies
Kshitij_Intel
Employee
1,280 Views

Hi,

 

You can use the "Native Fixed Point DSP Intel Stratix 10 FPGA IP".

MicrosoftTeams-image (9).png

Thank you

Kshitij Goel

 

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Navaneeth
Novice
1,265 Views

Hi,

Thanks for the reply.

 

We modified our Verilog code and introduced registers at the appropriate places by looking at the circuit diagram of the 'Native Fixed Point DSP Intel Stratix 10 FPGA IP'. The latency from input to output is 5 clock cycles with the modified code. Now, Quartus is saying that all the DSP blocks, that it is inferring, are fully utilizing the recommended internal register banks.

 

Please find the modified MAC unit Verilog code:

Version_4.png

 

Please do suggest further improvements, if any, to achieve higher Fmax.

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Kshitij_Intel
Employee
1,246 Views

Hi,

 

You can also check the full design template within Quartus.

 

Capture.PNG

 

Thank you

Kshitij Goel

 

 

 

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Navaneeth
Novice
1,209 Views

Thanks for the information.

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