FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5748 Discussions

DSP Builder IP generator Error - help please

Altera_Forum
Honored Contributor I
814 Views

Hi 

 

I am using DSP Builder 11. When I am trying to compile my design, the Quartus error I receive is: 

 

Error: IP Generator Error: Entity ' ' (Version latest) not found in librarian. 

 

I found a note in the Altera Web site regarding this issue but it is not relevant to me, as I do not have such a folder (.altera.quartus). (could this be the problem?) 

 

Any help to at least of the above question will help me a lot. 

 

Thank you in advance, 

 

Ahmed
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
68 Views

The .altera.quartus problem went away a few years ago. You shouldn't see it with DSP Builder 11.0. 

 

Do you see this problem with any design or just one in particular? Try creating a very simple design with just an input port connected to an output port and see if that compiles.
Altera_Forum
Honored Contributor I
68 Views

Do you use a imported Megacore or VHDL code? If this is the case run 

 

alt_dspbuilder_refresh_HDLimport 

 

for imported VHDL code or 

 

alt_dspbuilder_refresh_megacore 

 

for imported Megacore in the Matlab command window to rebuild the dependencies for these blocks.
Reply