FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5946 Discussions

DSP Builder Signal Compiler Error

Altera_Forum
Honored Contributor II
797 Views

I have a model that gets all the way through the compilation and programming process but then freezes after the message that the programmer action is complete. I have left it at this point for 2.5 hours with no change and I have no idea what could be causing it. I have been able to program simpler designs with no problem but as soon as I put an FIR megablock in the model I get this error.

0 Kudos
0 Replies
Reply