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Does any one have a model design in simulink of a DUC (digital up converter)and DDC that ca be implemented in a Cylone III FPGA.
Is there a reference design or example to interface this design with a HSMC (High Speed Mezzanine Card) I am trying to implement a IF stage with a CycloneIII devise. I am new in this technology so any advise, reference design, IP, etc will be appreciated very much ArmandoLink Copied
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Altera has been showcasing DSP Builder Advanced Blockset for Simulink to do DUC. there are design examples included with the tool
they won't be targeting a specific board with HSMC, you'll have to build a project around the DUC
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