I work on a project that generates a test pattern and display it on a DVI monitor with Arria 10 SoC board. I am using Quartus 18.1. I used HDMI Intel Arria 10 FPGA IP Design Example as a base. My project is supposed to be TX-Only version of the design example. So I generated a test pattern which is 1024x768/60fps; and connect the vid_data(95:0), vid_de(1:0), vid_hysnc(1:0), vid_vsync(1:0) signals to hdmi_tx_top block's input. These are the some of the other inputs of hdmi_tx_top block:
- mgmt_clk <= 100 Mhz FPGA clock
- hdmi_clk_in <= 65 Mhz clock from the pll
- reset <= not(locked)(pll_lock of the 65 mhz pll)
- reset_pll_reconfig <= not(locked)
- reset_xcvr <= not(locked)
- reset_pll <= not(locked)
- os <= "11" (constant since the oversample factor should be 5 due to the example design user guide page 65)
tx_core_top(under the hdmi_tx_top) block is working properly where I can see it from signal tap. Its "mode" input is contant '1' so it can be work as DVI interface. It generates 80 bits parallel data(tx_parallel_data(79:0)). And this signal is input of the gxb_tx block which is the transceiver native phy. The output of this block is a 4-bit signal where the bits are red,green,blue and clock(tx_serial_data(3:0)). It is connected to the dvi pins. But I cant see anything on the monitor. There is no output, no signal. I think I configured the transceiver native phy IP in a incorrect way.
These are the configurations that I made on qsys:
- Transceiver configuration rules: Basic/Custom(Standard PCS)
- PMA configuration rules: basic
- Transceiver mode: TX Simplex
- Number of data channels: 4
- Data rate: 3900
- ✔️ Enable simplified data interface
I calculated data rate like this:
(1024 x 768) x 60 x 40(r+g+b+c) x 2(symbol per clock) = 3.77 Gb ~ 3.9 Gb.
So the transceiver pll should generate 1950 Mhz clock and it does.
The inputs of the transceiver native phy:
- tx_coreclkin(3:0) <= tx_clk(0)&tx_clk(0)&tx_clk(0)&tx_clk(0)(tx_clk(3:0) is output of the transciever, so it uses its own output as an input)
- tx_analog_reset <= output of the transceiver reset block's tx_analog_reset
- tx_digital_reset <= output of the transceiver reset block's tx_digital_reset
- tx_bonding_clocks(23:0) <= gxb_tx_bonding_clocks&gxb_tx_bonding_clocks&gxb_tx_bonding_clocks&gxb_tx_bonding_clocks(transceiver pll bonding clock output)
- tx_polinv(3:0) <= "0000"
- tx_parallel_data(79:0) <= output of tx_core_top
What should I might be doing wrong? Please help, I am stuck.
Since you are using the example design (ED) as a baseline, why not you follow the User Guide to generate the RX-TX re-transmit design then follow the step to remove the component for TX-only design.
I checked your HDMI/Native PHY IP setting, I found that for Native PHY, the data rate for ED is 6000 Mbps while you are using 3900Mbps. Maybe as a quick check, you can try to change the data rate to 6000 Mbps and try.
I summarize the suggestion as below:
1. Change the transceiver data rate to 6000 Mbps.
2. Generate the Tx-Rx design, remove the RX and other components as stated in UG. Integrate the customer video source and try.
3. If your board has the Rx channel, build the Rx-Tx design, connect Rx from external video source see it can re-transmit the video.
4. Connect the reset signal to a toggling button or ISSNP. So that you can toggle it when connecting to a monitor see if the display works after reset.
5. Upgrade the design to latest version, at least 19.4.
Last thing is how you determine the dmi_clk_in is 65Mhz? I generate the example design target Arria 10 development kit, the frequency is 300MHz.
Hello @BoonT_Intel ,
Thank you for your attention. I have tried 6000 Mbps for transceiver data rate and it didnt work. I haven't tried the Tx-Rx Design but my design is the version of removed RX and unnecessary components as explained in the user guide. In the user guide it says that the frequency of the hdmi_clk_in signal should be the same as TMDS Clock frequency. I have checked the internet for the pixel clock of the resolution 1024x768/60fps and it is 65 MHz. I thought it is also the TMDS Clock Frequency. Am I wrong about that?
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