I have set up a design with two TSE MAC's and trying to send data from the first MAC to the second MAC. But somehow the data gets corrupted on the first TSE MAC and doesn't appear as it should be on the FIFO_RX interface.
The data that I provide on the RGMII RX in my Testbench appears to be fine in the simulation.
I have configured the MAC in RGMII mode in 100MBps.
The register clock, rgmii clock and fifo clocks are set to 25MHz.
Could anyone help me out please?
- Intel® Ethernet
Thanks for replying, I am using the Intel Triple-Speed Ethernet IP for the two MAC's. So yes it's an Ethernet controller.
I have already solved the problem with the FIFO, it was something with setting the registers of the TSE MAC.
I do have another question
I am trying to upload this design on my MAX10 FPGA. Do you know if i could leave out the PHY configuration in RGMII mode so the TSE MAC would use auto negotiation to communicate to the PHY?
For now I got only one Ethernet port working, by using the "MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User Guide"