Dear Sir, just before 15 days we got ARRIA10GX development kit . 1.We connected bitec FMC HDMI connector RECEIVER sink to PC GPU GTX1050. and connected 4k tv to the transmitter side.

[SDasa2]

when we loaded the precompiled sof file to the kit --- in nvide control panel its detecting the arria10gx card. but there is no display on source -4K TV.

we installed quartus prime 17.1 pro and the desing is

 AN 776: Intel® Arria® 10 UHD Video Reference Design.

2. we have to use HDMI RX AND TX IP CODE DDR4 MEMORY WITH SOME LOGIC TO BE IMPLEMENTED IN THE CODE . I know vhdl language. not familiar verilog.

also not familiar with NIOS2 . SO FOR IMPLEMENTATION OF OUR LOGIC 

WHICH IP CORES I HAVE TO USE .

pls give us the solution .

[BoonT_Intel]

Hi Do you have chance to observe the LED status and try to change the resolution by pressing the button PB0,1 and 2?

As explained in Table 2 and 3 of the AN. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an776.pdf

[SDasa2]

Hi, Sir, PROGRAMMED THE FPGA with master image file and when PB1 is pressed RED LED 7 is glowing. and when again pressed its not glowing. .From NIos2 command shell when running build_sw.sh fatal error . for files its telling permission denied.. and make failed condition arrived. ITS TELLING NO SIGNAL ON MONITOR . and display is blanking thanks and regards D.SUVARNA MIC ELECTRONICS LTD.

[BoonT_Intel]

Hello,

can you share a screenshot how it show permission denied and make failed condition arrived.

And also where its tell no signal on monitor.

Thanks

[SDasa2 · Accepted solution]

Hi Sir, I installed quartus19.3 prime pro version and while generating the example design THE WARNING MESSAGE CAME ABOUT NIOS 2 SOFTWARE CAN NOT BUILT. image attached. HDMI Intel® FPGA IP User Guide Updated for Intel® Quartus® Prime Design Suite: 19.3 in this datasheet page no 4 : related information arria10 gx example design link shows the following information on first page HDMI Intel® Arria 10 FPGA IP Design Example User Guide Updated for Intel® Quartus® Prime Design Suite: 18.1.. *I generated design example in 19.3 AND COMPILED * *1. which quarus prime version i have to instal ?* *2. compilation time is 40 minutes . how can we reduce compilation time? * *after loading sof file sink detection is not there .*

[BoonT_Intel]

hi, I don't see any attachment. Can you please attach again. Also, based on your current description, it seem like completely different with what you reporting in the beginning. Please confirm what is the actual issue that you are facing now.

[SDasa2]

Hi Sir, Our FAE is in contact with INTEL he raised a case, for the same kit. as per his suggestion as uhd design is complicated version he told to refer a design hdmi tx_rx retransmit i will attach data sheets . so i installed quartus 19.3 prime pro version and for this we have to install NIOS2 ide MANUALLY HENCE WHICH VERSION OF NIOS 2 I HAVE TO INSTALL? I CREATED THE EXAMPLE DESIGN AND LOADED THE SOF FILE . BUT ONE OF THE GRN LED "D8" LED IS BLINKING CONTINUOUSLY. IF I FOUND THE TX RX DATA PATH OK I HAVE SOME DOUBT ON MY DESIGN I WILL INFORM U ABOUT THAT. *Quartus Prime (includes Nios II EDS)* *Size:* 2.8 GB *MD5:* 7C1CDF9CEDCB81C730C5EC3BE15F6398 ** Nios II EDS on Windows requires Ubuntu 18.04 LTS on Windows Subsystem for Linux (WSL), which requires a manual installation. ** Nios II EDS requires you to install an Eclipse IDE manually. HENCE WHICH VERSION OF NIOS 2 I HAVE TO INSTALL? SO AS PER YOUR OPINION WHICH TOOL I HAVE TO INSTALL? PLS CLEAR MY PROBLEM AS IT IS VERY URGENT FOR OUT TESTING PURPOSE THANKS AND REGRDS d.suvarna

[BoonT_Intel]

Hi Sir,

See the instruction from this link for the IDE installation

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/why-does-the-nios--ii-not-installed-after-full-installation-of-t.html

[SDasa2]

Hi Sir, as per this links I installed nios2 _eclipse and crated example design again .

[SDasa2]

ATTACHED OTHER IMAGE RED MARK DURING COMPILATION .

[BoonT_Intel]

Hi Sir,

What do you mean by red mark during compilation? is it compilation error?

I don't see any image attach here.

[SDasa2]

Dear Sir,

as per the links attached by u, I installed nios2 _eclipse and crated example design again .

1.eclipse-cpp-mars-2-win32-x86_64

2.quartus-19.1-0.02-linux.run

I am attaching the images again.

still the warnings came after example design creation. and other one is after compilation warning

[SDasa2]

Dear Sir, during example generation creation this warnings came. warning : hdmi_0 : window subsystem for linux (WSL) is not installed. warning : hdmi_0 : nios software will not be built. and after compilation : warning TCL script file : software/tx control /mem init/mem_init.qip not foud. i loade the sof file one of rx status green led blinking. pls give the solution immediately.

[BoonT_Intel]

Here, here is the step to install WSL

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/how-do-i-install-the-windows--subsystem-for-linux---wsl--on-wind.html

[SDasa2]

Dear Sir, I installed quartus prime pro version 18.1 and generated TX_RX example design whatever display is coming from GPU source is displaying in SINK MONITOR. NOW- we have to use HDMI RX AND TX IP CORE AND DDR4 MEMORY WITH SOME LOGIC TO BE IMPLEMENTED IN THE CODE . I KNOW VHDL LANGUAGE AND NOT FAMILIAR WITH VERILOG AND NIOS2 SOFTWARE. SO FOR IMPLEMENTATION OF OUR LOGIC WHICH IP CORES I HAVE TO USE . IS NIOS2 COMPULSORY . HOW SHOULD I PROCEED .

[BoonT_Intel]

Regarding using which IP cores, it is depend on your application needs. I can't tell you which IP that you need without knowing your needs.

By the way, quartus also support VHDL.

[SDasa2]

i am using quartus 17.1 pro version pls find the attached txt file for nios 2 build its teeling permission denie

[BoonT_Intel]

Hello,

Are you posting this note in correct thread? Previously you did mentioned that the design is already work in 18.1. Then now you mentioned about 17.1. What is the problem that you facing in 17.0? I don't see you attach anything. Please note that you should stick on latest quartus version. Only latest 3 quartus version is officially supported.

[SDasa2]

dear sir, as UHD example design is in quaratus prime pro 17.1 i want to test that example design . but when running script in nios2 shell in 17.1 i am getting errors. . just i created tx_rx retransmit example design in version 17.1 the following errors are coming. please see highlighted text in red color below .

[BoonT_Intel]

Hello,

Again, I don't see any highlighted text.😥

[SDasa2]

MIC COLLEGE@DESKTOP-4M4AAL3 /cygdrive/f/intelFPGA_pro/projects_17_12_19/HDMI_TEST_171/hdmi_0_example_design/script $ ./build_sw.sh cp: cannot create regular file './../software/tx_control/i2c.c': Permission denied cp: cannot create regular file './../software/tx_control/i2c.h': Permission denied cp: cannot create regular file './../software/tx_control/main.c': Permission denied cp: cannot create regular file './../software/tx_control/xcvr_gpll_rcfg.c': Permission denied cp: cannot create regular file './../software/tx_control/xcvr_gpll_rcfg.h': Permission denied