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Altera_Forum
Honored Contributor I
723 Views

Debugging Arria GX DDR2 Controller

I am using an ArriaGX EP1AGX90EF1152 to control 4 x MT47H128M16 SDRAM chips. The controller is the DDR2 SDRAM High Performance Controller v9.0 Build 235. Memory clock frequency i2 162MHz and PLL Ref Clock is 27MHz. 

The controller works well and I have been using it for medium quantity production for several years. 

My problem is in production debug area. The SDRAM fails to initialise and the "init_done" output from the controller remains low. 

How does the controller decide that initialisation is incomplete. 

The 27MHz clock is present inside the Arria. 

Short of replacing all the memories and the Arria is there any way I can localise the problem.  

NOTE: this only occurs in 1 board out of several hundred .
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2 Replies
Altera_Forum
Honored Contributor I
33 Views

Hello, 

 

Did you use the Debug Toolkit for DDR2 and DDR3? 

Look at the "External Memory Interface Handbook Volume 4 Section III. Debugging" 

I used it to fix few boards. 

 

Good luck, 

Reuven
Altera_Forum
Honored Contributor I
33 Views

 

--- Quote Start ---  

Hello, 

 

Did you use the Debug Toolkit for DDR2 and DDR3? 

Look at the "External Memory Interface Handbook Volume 4 Section III. Debugging" 

I used it to fix few boards. 

 

Good luck, 

Reuven  

--- Quote End ---  

 

Hi Reuven, 

 

Thanks for your help. 

I have not used the Debug Toolkit for DDR2 and DDR3, but I will try it as soon as I can get back to the production debug project. 

 

Regards, 

Brian
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