FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Debugging PC Express hard IP core

Altera_Forum
Honored Contributor II
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Hi all, 

 

 

I've got a link up (ltssmstate = L0) - and external device sees the link but still I don't see any data going out from hard IP core. How can I debug and see whether anything is coming to Hard IP and/or get discarded?  

 

Best regards, 

Dominik
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