FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Decoder IP problem

Altera_Forum
Honored Contributor II
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HI,  

I want to know how to do with that problem in the decoder IP ( Reed Solomon and Viterbi), it is the same problem. "all the output are zero ". 

can anyone help me please? I am really in a big trouble
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Altera_Forum
Honored Contributor II
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I know that this may be late for you lolitta73, however it may be useful for future visitors. 

Recently I have had the same behavior and the problem was that at one point (normally few seconds after starting decoding process) I was sending into the module two consecutive StartOfFrame signals without EndOfFrame signalling in between. And now you can use SignalTap in order to scope the problem! ;)
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