FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Decoder IP problem

Honored Contributor II


I want to know how to do with that problem in the decoder IP ( Reed Solomon and Viterbi), it is the same problem. "all the output are zero ". 

can anyone help me please? I am really in a big trouble
0 Kudos
1 Reply
Honored Contributor II

I know that this may be late for you lolitta73, however it may be useful for future visitors. 

Recently I have had the same behavior and the problem was that at one point (normally few seconds after starting decoding process) I was sending into the module two consecutive StartOfFrame signals without EndOfFrame signalling in between. And now you can use SignalTap in order to scope the problem! ;)