Description of QSYS example design IP: PCIe DMA Controller 64/128 bit.

[Waveform]

Hello!

Please, help me with QSYS example design IP: PCIe DMA Controller 64 bit.

I need to make a simple DMA exchange between Arria10 (EP) and CPU (RC) onboard thru PCIe Gen3 x1 link. Because of x1 I couldn't use of PCIe internal DMA controller. So, I've found design example ep_g2x1_avmm64 with PCIe DMA Controller 64. The question is, where can I found description of control port slave registers of DMA Controller 64?

Of couse, I have source files of that IP, but maybe it is described somewhere.

[AnandRaj_S_Intel]

Hi Andrey,

You can refer to the design example from below link.

https://forums.intel.com/s/createarticlepage?articleid=a3g0P0000005RPeQAM&action=view

https://forums.intel.com/ics-frm-article/a3g0P0000005RPUQA2/reference-design-gen3x8-avmm-dma-arria-10?articleid=a3g0P0000005RPUQA2&action=view

Regards

Anand

[Waveform]

Mentioned example is not suitable for me, because I have only one x1 PCIe link. High performance embedded DMA controller doesn't support this case. I have found by my self appropriate example:

https://forums.intel.com/s/contentdocument/0690P000004pfl4QAA

[AnandRaj_S_Intel]

Hi Andrey,

Presently we dont have any example with PCIe Gen3 x1.

Those links are for reference only.

You have change the parameters in IP's as per your requirements.

Regards

Anand

[PaulR1]

Hi Anand,

The links posted are no longer live, are there any descriptions of how to use these example systems.  I have the same issue as Andrey in that the PCIe Hard IP with DMA doesn't support the lower version (and number of lanes) of IP that my customer requires.   

I need to provide a PCIe Gen1x1 with DMA and am looking for the most suitable solution.   Where are these examples described so that I can modify or use correctly ?

Thanks and Best Rgds

Paul 

[scs-kno]

Any luck with the PCIe DMA Controller 64 (altera_avalon_dma_pci)?

PS: The DMA core is described in Embedded Peripherals IP User Guide in Chapter 30. Adapt TXS connections to read xor write from host memory to a destination.