Please, help me with QSYS example design IP: PCIe DMA Controller 64 bit.
I need to make a simple DMA exchange between Arria10 (EP) and CPU (RC) onboard thru PCIe Gen3 x1 link. Because of x1 I couldn't use of PCIe internal DMA controller. So, I've found design example ep_g2x1_avmm64 with PCIe DMA Controller 64. The question is, where can I found description of control port slave registers of DMA Controller 64?
Of couse, I have source files of that IP, but maybe it is described somewhere.
You can refer to the design example from below link.
Mentioned example is not suitable for me, because I have only one x1 PCIe link. High performance embedded DMA controller doesn't support this case. I have found by my self appropriate example:
Presently we dont have any example with PCIe Gen3 x1.
Those links are for reference only.
You have change the parameters in IP's as per your requirements.