Im a newbie to FPGA design. Im designing a matrix multiplication component (6X6). The matrix component takes in input and params to calculate the output. The input and params should be read from the BRAM and the output has to be stored in the BRAM memory. The params which is a 6X6 matrix has to be stored in a double buffer where the active values will be placed in a front buffer and the remaining param set will remain the back buffer. I would like to know if the data input, param set has to be designed as a separate components or it has to be within the matrix multiplication component ?
Note: The Serial Rapid IO interface IP core will be writing the input from the processor to the application memory address. The accelerator is supposed to read these values and perform the calculations.
Arria 10 dev kit
Host : power PC
Interface : serial rapid IO
Tools : Quartus Prime Pro + HLS compiler
Kindly help me.
Thanks in advance
Thanks for your update. For your information, it is rather difficult for me to comment on a design implementation. However, as I look into the Quartus IP Catalog, I come across this ALTERA_FP_MATRIX_MULT IP. Probably you could explore in this to see if it fit your requirement.