Didital Down Converter

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Didital Down Converter

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Hello.

I am developing the DDC (Digital down converter).

I am using standard Altera IP core (NCO, CIC, FIR).

Signal after mixer, decimate by CIC (decimation coefficient 1920) and then by FIR (decimation coefficient 2) [Please see the attached file].

1) CIC_out_valid signal using us clock for FIR filter. Is it correct ?

2) Please tell me how to constraint the LRCK_32KHz Port. [SDC File is attached]

I am hope for your help.

Thanks.

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