I am developing the DDC (Digital down converter). I am using standard Altera IP core (NCO, CIC, FIR). Signal after mixer, decimate by CIC (decimation coefficient 1920) and then by FIR (decimation coefficient 2) [Please see the attached file]. 1) CIC_out_valid signal using us clock for FIR filter. Is it correct ? 2) Please tell me how to constraint the LRCK_32KHz Port. [SDC File is attached] I am hope for your help. Thanks.