I have designed a custom DMA controller for a Qsys-based PCIe design I have been working on. The stock SG-DMA (and MSGDMA) controllers did not have quite the correct behavior, so I wrote a custom controller. I made the PCIe TXS port a conduit and connected the Qsys ports to the custom DMA controller. It currently supports only DMA writes to the PC memory, since that is all we need at this time.I have simulated the controller by itself, and the behavior on the TXS signals appears to be correct: * txs_chipselect idles low, goes high on the first write cycle, and goes low after the last write cycle * txs_burst count idles at 0, is set to 32 on the first write cycle, and goes to 0 when complete * txs_address is set up on the first write cycle and stays constant for the entire burst. I have it loaded with a QWORD aligned 32-bit physical address on the PC. * The PCIe address translation table is set up with one fixed entry mapping Avalon-MM address 0 to PCIe address 0. * txs_write goes high on the first write cycle, and stays high until complete * If txs_waitrequest goes high, the state machine does not decrement the internal burst count * txs_byteneable is set to 8'hff on the first write cycle and resets to 0 when done I tested the address translation and physical address setup with a version based upon the SG-DMA core. I built a debug mode into the controller to disable the TXS outputs and ignore txs_waitrequest. Using this mode, I could verify that the state machine will complete the mock transfer. However, when debug mode is disabled, the burst counter does not increment. So, it appears that waitrequest is being asserted. I'm looking into that some more. I have two main questions. First, am I misinterpreting the Avalon-MM bus signals? I don't see any timing diagrams, so I'm not sure if I should set up the address, chip-select, burst-count, or anything else before the write begins. The second question is about the address space on the txs_address bus. Qsys generates a [31:0] port for the txs_address conduit. Is this a QWORD address or a byte address?