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Discontinuity in the read data burst - quarter rate DDR3 SDRAM controller

Altera_Forum
Honored Contributor II
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I have a quarter rate DDR3 SDRAM controller on an Arria V FPGA. I see discontinuity in the read data burst (only every 5th clock I get new data). I found an applicable article in the knowledgement base (solution ID rd10132011_912) which says I should manually update CFG_RDBUFFER_ADDR_WIDTH in alt_mem_ddrx_controller.v to "6" (now as written in map.rpt file it has a value of 7). But as I have the memory controller embedded in a QSYS system this is an output file from QSYS and therefore changes are overwritten by the system. How can I change this parameter in a QSYS system? 

 

Some project details (maybe there are other reasons for the discontinuity): 

· DDR3 SDRAM Controller with UniPHY, Version 13.1 

· Memory clock frequency: 300 MHz 

· Quarter rate Avalon-MM interface (resulting in an achievable local clock frequeny of 75.0 MHz) 

· Memory width: 32 bit (Avalon width 256 bit due to quarter rate) 

· Maximum Avalon-MM burst legth set to 256 

· Local-to-Memory Address Mapping: CHIP-ROW-BANK-COL (I have two 16 bit DDR3s connected, Micron MT41K256M16HA, available within dropdown list) 

· Actual avalon clock rate: 55 MHz 

· Device: Arria V GX 5AGXBA1D6F27C6 

· Memory works
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