DisplayPort IP Example Design - VHDL

[DZuck1]

Hi,

I am trying to use Quartus Prime 17.0 to generate the DisplayPort IP Example Design for VHDL simulation.

I followed through the directions in the UG (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-dp-de-17-0.pdf) to generate the example design and to simulate it in Aldec. The directions worked and I was able to run through the entire simulation in Aldec with minor edits to the simulation scripts. The only issue is that I asked Qsys for VHDL files but the testbench and top level design files generated were both Verilog.

I selected VHDL from the drop down menu. Am I doing something wrong or is there a bug in the example design generator?

Thanks,

Daniel

[Vicky1]

Hi,

I also realized same behavior, let me check internally with team & get back to you.

I could observe following two things which indicates that DisplayPort IP Example Design available only in Verilog HDL.

• check the Figure 2. & Table 1. from the link below

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-dp-de-17-0.pdf

• check screenshot of Warning message during generation,

Regards,

Vikas Jathar

[DZuck1]

Hi Vikas,

It looks like Verilog is the only one supported based on Figure 2 and Table 1 but Table 21 says that VHDL is supported.

Thanks,

Daniel

[Vicky1]

Hi Daniel,

Yes, It supports for vhdl & verilog but presently available in verilog only.

Regards,

Vikas