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Michael2021
Beginner
73 Views

DisplayPort at non GPU mode on Cyclone 10 GX and Quartus pro 20.1

I tried to finalize design non GPU mode. doesn't provide non GPU mode example design.  I can't figure it out  how to connection Transceiver Native PHY Reconfiguration interface signal ( this signal is not in Arria V GX and there is av_xcvr_reconfig IP in Arria V GX).  For PHY reconfiguration, I tried to use bitec_reconfig_alt_c10. 

Can you advice PHY reconfiguration signal connection on non GPU mode?

  

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7 Replies
Deshi_Intel
Moderator
54 Views

Hi,


My understanding is GPU mode vs none-GPU mode should only affect DisplayPort IP DPCD setting and shouldn't affect transceiver design connection.


Have you looked into DisplayPort GPU mode example design to study the transceiver connection ?


Thanks.


Regards,

dlim


Michael2021
Beginner
45 Views

In non GPU mode, there is no CPU  so, can't drive bus. But still there is CPU bus and do I leave it no connection ?

thank you

Michael

Deshi_Intel
Moderator
34 Views

Attached is the DP Rx CPU bus connection with GPU mode on or off 

Deshi_Intel
Moderator
33 Views

Hi,


With refer to my previous post update and attached screenshot, I do see DP Rx CPU bus is removed when GPU mode is turned off in Quartus Pro v20.1


Are you seeing different result than me ?


Regards,

dlim





Michael2021
Beginner
21 Views

I knew I got  the same result in non GPU mode on DP core. My question is not DP core. Transceiver reconfiguration connection has GPU bus. 

How to connection this three files in non  CPU mode ?

bitec_reconfig_alt_c10.v,   xcvr_reconfig_arbiter.sv,  av_native_phy_rx.ip.

and where is  .mif file or no need .mif file ?

thank you

Michael

Deshi_Intel
Moderator
18 Views

Hi Michael,


Ok, I understand your confusion now.


Just to clarify, those transceiver reconfiguration bus are not GPU port and has nothing to do with DisplayPort GPU mode.

  • These are just transceiver NativePHY IP Avalon MM port exposed to user design to allow user to perform dynamic reconfiguration process to change transceiver data rate
  • How the dynamic reconfiguration control coding is done is really up to user itself. It can be in the form of RTL state machine or NIOS CPU C- code design
  • You can refer to chapter 6 of below doc for explanation of transceiver dynamic reconfiguration process


In C10 GX DP example design, the dynamic reconfiguration control RTL state machine coding design is located in bitec_reconfig_alt_c10.v and xcvr_reconfig_arbiter.sv as you mentioned.

  • The MIF file is prebuild dynamic reconfiguration file for ease of transceiver data rate switching.
  • For example : mif file location
  • <DP example design>\rtl\rx_phy\gxb_rx\altera_xcvr_native_a10_xxx\synth\reconfig


The difference between DP IP Rx GPU mode on/off is as below

  • GPU mode on : user has flexibility to control DP DPCD register space initialization in software like CPU C-code
  • GPU mode off : DP DPCD register is hardcoded in DP Sink IP


So whether DP Sink IP GPU mode is off or on, it shouldn't affect your transceiver channel connection. I visualize the system design connection as below

  • DP Sink IP <-> Transceiver Rx NativePHY IP <-> additional dynamic reconfig design


Thanks.


Regards,

dlim



Michael2021
Beginner
14 Views

Thank you

I understand GPU mode on/off function clearly.

I look at bitec_reconfig_alt_c10.v  It doesn't have  .mif file reading function. 

If I need  more information , I will let you know.

Thank you again

Michael