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5878 Discussions

DisplayPort at non GPU mode on Cyclone 10 GX and Quartus pro 20.1

Michael2021
Beginner
1,191 Views

I tried to finalize design non GPU mode. doesn't provide non GPU mode example design.  I can't figure it out  how to connection Transceiver Native PHY Reconfiguration interface signal ( this signal is not in Arria V GX and there is av_xcvr_reconfig IP in Arria V GX).  For PHY reconfiguration, I tried to use bitec_reconfig_alt_c10. 

Can you advice PHY reconfiguration signal connection on non GPU mode?

  

0 Kudos
21 Replies
Deshi_Intel
Moderator
1,108 Views

Hi,


My understanding is GPU mode vs none-GPU mode should only affect DisplayPort IP DPCD setting and shouldn't affect transceiver design connection.


Have you looked into DisplayPort GPU mode example design to study the transceiver connection ?


Thanks.


Regards,

dlim


Michael2021
Beginner
1,099 Views

In non GPU mode, there is no CPU  so, can't drive bus. But still there is CPU bus and do I leave it no connection ?

thank you

Michael

Deshi_Intel
Moderator
1,088 Views

Attached is the DP Rx CPU bus connection with GPU mode on or off 

Deshi_Intel
Moderator
1,087 Views

Hi,


With refer to my previous post update and attached screenshot, I do see DP Rx CPU bus is removed when GPU mode is turned off in Quartus Pro v20.1


Are you seeing different result than me ?


Regards,

dlim





Michael2021
Beginner
1,075 Views

I knew I got  the same result in non GPU mode on DP core. My question is not DP core. Transceiver reconfiguration connection has GPU bus. 

How to connection this three files in non  CPU mode ?

bitec_reconfig_alt_c10.v,   xcvr_reconfig_arbiter.sv,  av_native_phy_rx.ip.

and where is  .mif file or no need .mif file ?

thank you

Michael

Deshi_Intel
Moderator
1,072 Views

Hi Michael,


Ok, I understand your confusion now.


Just to clarify, those transceiver reconfiguration bus are not GPU port and has nothing to do with DisplayPort GPU mode.

  • These are just transceiver NativePHY IP Avalon MM port exposed to user design to allow user to perform dynamic reconfiguration process to change transceiver data rate
  • How the dynamic reconfiguration control coding is done is really up to user itself. It can be in the form of RTL state machine or NIOS CPU C- code design
  • You can refer to chapter 6 of below doc for explanation of transceiver dynamic reconfiguration process


In C10 GX DP example design, the dynamic reconfiguration control RTL state machine coding design is located in bitec_reconfig_alt_c10.v and xcvr_reconfig_arbiter.sv as you mentioned.

  • The MIF file is prebuild dynamic reconfiguration file for ease of transceiver data rate switching.
  • For example : mif file location
  • <DP example design>\rtl\rx_phy\gxb_rx\altera_xcvr_native_a10_xxx\synth\reconfig


The difference between DP IP Rx GPU mode on/off is as below

  • GPU mode on : user has flexibility to control DP DPCD register space initialization in software like CPU C-code
  • GPU mode off : DP DPCD register is hardcoded in DP Sink IP


So whether DP Sink IP GPU mode is off or on, it shouldn't affect your transceiver channel connection. I visualize the system design connection as below

  • DP Sink IP <-> Transceiver Rx NativePHY IP <-> additional dynamic reconfig design


Thanks.


Regards,

dlim



Michael2021
Beginner
1,068 Views

Thank you

I understand GPU mode on/off function clearly.

I look at bitec_reconfig_alt_c10.v  It doesn't have  .mif file reading function. 

If I need  more information , I will let you know.

Thank you again

Michael

 

Michael2021
Beginner
1,049 Views

Hi

I changed  non GPU and rx_phy only mode in dp_0_ example_design and added EDID memory. and Programming FPGA ( 10CX220YF672E6G) in custom board.

Windows 10 recognized new display (1920x1200, 120HZ, Attached pic1). but generated error (attached pic2).

I probed 5 inside signals

  1. gxb_rx_analogreset [0]  = always "1"

  2. gxb_rx_digitalreset [0]   = always "1"

  3. gxb_rx_analogreset_ack[0]   = always "0"

  4. rx_analog_reconfig_req   = always "0"

  5. rx_reconfig_busy    = always "1"

 

I think the digitalreset and analogreset doesn't release,

so  it doesn't works transceiver configuration. 

Can you recommend any solution ?

Thanks

Michael 

Deshi_Intel
Moderator
1,029 Views

Hi,


Yup, looks like your design DP link transceiver channel is stuck in reset.


Transceiver NativePHY IP reset operation is managed by another IP called "transceiver PHY reset controller" IP.

  • There is one master reset input pin to this reset controller IP.
  • You may want to slowly trace back in your design how does this master reset input pin is connected and make necessary design modification. If reset controller is held in reset then your transceiver channel will be stuck in reset as well


Thanks.


Regards,

dlim


Michael2021
Beginner
1,026 Views

Thanks for recommending.

I look at the rx_phy_top.v. I think they have three reset (cpu_reset_n, cpu_reset, video_pll_locked). all three signal is good signal input from external  module.

Can you recommend any other signals to solve this ?

I have experience of DP design using Arriva V GX. I knew  transceiver reconfiguration module have many different signal as compare with Arria V GX.  I can't guess how to work configuration mechanism in Cyclone 10 GX. Does the CPU need to initialize rx_phy_top module after reset released ?

Thank you

Michael

 

Deshi_Intel
Moderator
1,007 Views

Hi,


Transceiver reconfiguration process itself is a complicated process so I don't have easy way to explain to you.


  1. To learn more about it - you can refer to C10 GX transceiver PHY user guide doc (chapter 6) that I shared with you in earlier post
  2. To look at actual design implementation example, bitec_reconfig_alt_c10.v is the reconfig controller example design that do all the magic trick. It's that complicated as you can see in the design file itself.
  3. For DP design implementation, you only touch on Transceiver reconfiguration process during below 2 phases (I believed below operation are controlled by bitec_reconfig_alt_c10.v)
  • During FPGA initial power up where you configure DP IP to operate at certain transceiver data rate
    • Whenever there is a need to change transceiver data rate, for instance DP link training process


The reset controller IP that I mentioned to you is below design module in rx_phy_top.v

  • gxb_rx_reset gxb_rx_reset_i (
    •  .reset        (reset | dp_rx_xcvr_reset | rx_restart_100),
  • You can signal_tap these 3 dependency reset OR signals to find out which one is causing the trouble and make necessary design changes


Thanks.


Regards,

dlim



Michael2021
Beginner
997 Views

Hi

When C10GX FPGA is power-up,

Does the CLKUSR pin need to be stable clock for PreSICE function, before FPGA configuration complete ?

Michael

Deshi_Intel
Moderator
984 Views

Hi,


Does the CLKUSR pin need to be stable clock for PreSICE function, before FPGA configuration complete ?

  • Yes. CLKUSR needs to be stable and free running clock before FPGA configuration started as this is the clock source used for FPGA power up transceiver channel calibration process.


Thanks.


Regards,

dlim


Michael2021
Beginner
980 Views

Thank  you

I didn't connect the clock at there.  Is there any solution how to skip this calibration process or should be there ?  I think that is different point than Arria V GX.

Michael

Deshi_Intel
Moderator
937 Views

HI,


This is bad.


Clkusr pin connection is a must as FPGA power up transceiver calibration process can't be skipped.

  • If transceiver channel is not calibrated correctly then it may affect the functionality later


I suggest you to rework your board to ensure there is proper clocking to clkusr pin.


Thanks.


Regards,

dlim


Michael2021
Beginner
933 Views

Ok, I understood.

The calibration process means internally storing some offset value.

Normally if the calibration doesn't work or can't be calculated, then default value is lorded and exited

But This case never can make it to work.

If the clock connect to there , then this is not failure decision (never can't make it to work) .  Is it right ?

I don't want to go back to use Arria V GX

I saw there is triggering calibration bit. Is this bit to skip calibration process ?

 

Thank you

Michael

Deshi_Intel
Moderator
925 Views

Hi,


Your understanding of general calibration process is correct that they are trying to calibrate certain offset value internally but my concern is without the clock, I am not sure whether the transceiver channel can be reverted to use back the default offset setting.


I worry the whole state machine design is stuck pending for clock source.


In your earlier debug signal capture ,

  • rx_reconfig_busy = 1
  • This is status signal to indicate completion of transceiver calibration process. It should de-assert low once calibration completed.
  • But right now looks like it's waiting for the missing clock and the whole calibration process is stuck forever


In proper operation, once calibration completed then only transceiver channel will be released from reset stage (gxb_rx_analogreset = 0, gxb_rx_digitalreset = 0)


I am not sure which calibration bit setting that you refer to but I am aware of only one register bit that we used to "trigger re-calibration process in FPGA user mode", not to skip calibration process


Regards,

dlim



Deshi_Intel
Moderator
867 Views

Hi,


Just to follow up, have you decided to fix the clkusr pin connection on your board ?


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
835 Views

HI,


I still have not hear back from you.


I will proceed to close case first as I can't let the case idle for too long. This thread will be transitioned to community support.


Yet, if you have fixed your board clkusr issue and would like to resume debug discussion in future, then feel free to post new forum post again to get support from Intel agent.


Thanks.


Regards,

dlim


Michael2021
Beginner
762 Views

Hi

I got the new board and Still doesn't work DisplayPort.

I attached two picture.

Picture 1 : cyclone 10gx transceiver PHY user Guide (20.1) page 259

Picture 1: I probing from my board.

In my system, the rx_is_lockedtodata signal is always low (it is problem)

Can you advice how to make it to work ?

My concern is rx_cal_busy and rx_analogreset signal is overlapping (?)

I didn't change anything in bitec-reconfig_alt_c10.v and xcve_reconfig_arbiter.sv.

  

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