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Altera_Forum
Honored Contributor I
819 Views

DisplayPort

Hi all, 

 

Normally the VESA mentions that the DP (with 4lines) is able to send 12-ppc YCbCr 4: 2: 2 (24 dpi) corresponding to 1920x1080p @ 120Hz  

I would like to know what will be the DTM (Display Monitor Timing) appropriate for it and the format of the video interface DP_Source (TX_VID_V, TX_VID_H,TX_VID_DE). 

The aim is to send a stream video from the Altera IP DisplayPort to the Altera IP HD-SDI. 

 

 

Thanks 

Regards, 

Hayder
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
60 Views

Afaik, SDI cannot do 120Hz. The Fastest format SDI is 3G-SDI (1080p @ 60Hz)

Altera_Forum
Honored Contributor I
60 Views

Hi Tricky, 

 

I Have read the user guide of DP and the specification of VESA to be able to implement this IP in my own design. I was able to run the design simulation of altera with modelsim. 

After that I created my owne design (DP-Sink plus thiers PHY and XCVR). The compilation passe without any error. But when I started the simulation of this design I have many error.  

1- When I take a look into the DISPLAYPORT_02_run_msim_rtl_vhdl.do file I found that many file didn't compiled (exp: altera_dp_reconfig_ctrl.v) 

2- The DP_SIM folder hadn't the entire file (altera_dp_reconfig_ctrl.v, altera_dp_reset_delay, altera_dp_status_sync). 

 

I am wondring why the quartus messed to include this file in the simulation folder. 

 

Thanks
Altera_Forum
Honored Contributor I
60 Views

I suggest raising a support request for help with specific cores.

Altera_Forum
Honored Contributor I
60 Views

Hi, 

I am trying to implement a converter of an DisplayPort-RX to HDSDI-TX. In the simulation the design has a good functionning but during the synthetise (Place and route) I got an error that told me that the design had HSSI PMA conflicts (The CALCLK must be driven by the same source). 

 

I am aware that the PHY-HDSDI and the PHY-DP have a different frequencies and I thought that the quartus will take this consideration to instantiate a different HSSI for each PHY. But when I got this error I am confiouse. and I thank one of the HSSI is used for RX Display and TX HDSDI and this way the conflit occurs.  

 

Now I am wondring if existe any special contraints to resolve this confilt ? 

 

thanks
ACont16
Beginner
60 Views

Hi,

I am trying to implement a converter of an DisplayPort-RX to 3DSDI-TX. Can you say me which ip core can i use?

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