Displayport Timing diagram for when setting Pixel input mode to Dual or Quad

[slmel]

Hi, 

We are planning to use displayport in out product. In this we need to know the timing diagram when setting Pixel input mode to Dual or Quad. According to user guide, 

1. Since 4 pixels are in parallel do we need to divide the data enable, horizontal sync, and
vertical sync signals also by 4?

2. If horizontal active, front porch, or back porch of a length not divisible by 2 or 4, how we extend above signals?

3. Do we need to extend all signals or particular signal?

Regards,

Sree

[Deshi_Intel · Accepted solution]

Hi,

1. For the video data transfer over single, dual and quad mode, you can look at at the high level timing diagram in below user guide doc (page 10 onwards - Figure 4,5,6)

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_hdmi.pdf

1. For understanding of detail transaction over certain video resolution across different video pixel mode

• I recommend you to build simple design connecting test pattern generator 2 (TPG2) IP -> Clock video output (CVO) II IP and configure the desired video resolution setting
  • Then run simulation to observe the sim waveform directly
  • You can learn more about TPG 2 and CVO 2 IP in below user guide (chapter 7 and chapter 22)
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_vip.pdf

Thanks.

Regards,

dlim

[slmel]

Thank you dlim for your support....

[Deshi_Intel]

You are welcome !