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Altera_Forum
Honored Contributor I
793 Views

Divider fail setup constraint

i can't meet constraints of a 64 bit divider, 

i added 64 stages of latency inside divider. 

 

How can i do?
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3 Replies
Altera_Forum
Honored Contributor I
48 Views

use a slower clock?

Altera_Forum
Honored Contributor I
48 Views

i found the problem!! 

 

if i disconnect the aclr, my divider setup slack increase noticeably! 

 

i think if a reset is inferred, more logic is required so this slow down the divider. 

 

if a reset isn't required, don't use it!!
Altera_Forum
Honored Contributor I
48 Views

i'm sorry i've not solved. 

if i disconnect the aclr, the whole divider is kept in reset! so the timing are right but unuseful. 

 

I tried to use a slower clock. I instantiated the PLL, the input of the PLL is Clock, the default signal.  

 

I made 2 Outputs and i would use these in DSP Builder, 

 

PLL_clk0 => 100MHz -- same frequency of Clock 

 

PLL_clk1 => 50 MHz 

 

am i right to run my design with the PLL_clk0 and the divider with the PLL_clk1 ?
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