FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

Divider fail setup constraint

Altera_Forum
Honored Contributor II
830 Views

i can't meet constraints of a 64 bit divider, 

i added 64 stages of latency inside divider. 

 

How can i do?
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
85 Views

use a slower clock?

Altera_Forum
Honored Contributor II
85 Views

i found the problem!! 

 

if i disconnect the aclr, my divider setup slack increase noticeably! 

 

i think if a reset is inferred, more logic is required so this slow down the divider. 

 

if a reset isn't required, don't use it!!
Altera_Forum
Honored Contributor II
85 Views

i'm sorry i've not solved. 

if i disconnect the aclr, the whole divider is kept in reset! so the timing are right but unuseful. 

 

I tried to use a slower clock. I instantiated the PLL, the input of the PLL is Clock, the default signal.  

 

I made 2 Outputs and i would use these in DSP Builder, 

 

PLL_clk0 => 100MHz -- same frequency of Clock 

 

PLL_clk1 => 50 MHz 

 

am i right to run my design with the PLL_clk0 and the divider with the PLL_clk1 ?
Reply