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Hello,
I'm using the Arria 10 Avalon Streaming PCIe IP as a root port, which Configuration Space Bypass enabled. I'm confused that is there still a virtual pci bridge beneth the avst port, awaiting to be configured using LMI or Type 0 Cfg Tlp?
The IP indicates that all well formed Tlp is forwarded to User Application Layer. Does this means that, with CfgBp enabled, the avst port is straightforwardly connected to the downstream EP, whose BDF can be arbitrary (no need to enumerate) as per PCIe Spec.
Thank you very much ~~
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Hi Lcy2000,
Thanks for reaching out.
Allow me some time to investigate your issue. I shall come back to you with the findings.
Thanks.
Best Regards,
Ven
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Hi Lcy2000,
When the Configuration Bypass (CfgBP) parameter is enabled, the Configuration Read/Write TLPs are output to the user side. The CfgWr1 and CfgRd1 TLPs are sent from the Root Port to the application layer, so the user circuit has to respond to those TLPs correctly.
In Configuration Bypass Mode, the hard IP passes all well-formed TLPs to the Application Layer using the Avalon-ST RX interface. The hard IP detects and drops malformed TLPs. Application Layer logic must detect and handle Unsupported Requests and Unexpected Completions. Application Layer logic must also generate all completions and messages and transmit them using the Avalon-ST TX interface.
I would suggest you to refer Stratix V Avalon-ST Interface for PCIe Solutions: User Guide for more information on Configuration Bypass.
Thanks.
Best Regards,
Ven
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Hi Lcy2000,
Do you have further questions on this thread?
Thanks.
Best Regards,
Ven
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Hi Lcy2000,
As there are no further inquiries, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.
After 15 days, this thread will be transitioned to community support.
The community users will be able to help you with your follow-up questions.
Thanks.
Best Regards,
Ven
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