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Does Altera SDR SDRAM Module support pipelined accesses or not?

Honored Contributor II

I'm confused ... :confused:  


Does the Altera SDR SDRAM controller support pipelined reads / writes or not? 


Up until today I've been under the impression that I needed to license a 3rd party SDRAM controller (SDR not DDR) to utilize burst mode accessing to improve my read/write speed on my SDRAMs (the clk rate is already topped out) ... 


Today, however, looking through the Altera SDR core datasheet ("one last time") it makes mention of pipelined accesses (page 1-2 of http://www.altera.com/literature/hb/nios2/n2cpu_nii51005.pdf): 



--- Quote Start ---  

avalon-mm interface 

The Avalon-MM slave port is the user-visible part of the SDRAM controller core. The slave port presents a flat, contiguous memory space as large as the SDRAM chip(s). When accessing the slave port, the details of the PC100 SDRAM protocol are entirely transparent. The Avalon-MM interface behaves as a simple memory interface. There are no memory-mapped configuration registers. 


The Avalon-MM slave port supports peripheral-controlled wait states for read and write transfers. The slave port stalls the transfer until it can present valid data. the slave port also supports read transfers with variable latency, enabling high-bandwidth, pipelined read transfers. When a master peripheral reads sequential addresses from the slave port, the first data returns after an initial period of latency. Subsequent reads can produce new data every clock cycle. However, data is not guaranteed to return every clock cycle, because the SDRAM controller must pause periodically to refresh the SDRAM. 


For details about Avalon-MM transfer types, refer to the Avalon Interface Specifications. 

--- Quote End ---  



... so I read up a bit more on Pipelined interfaces and see that pipelined accesses would work just as well as burst transfers in my case (sequential reads/writes), and I get excited...  


But now I'm really confused because the Avalon-MM Interface Specs (Figure 3.5 on http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) seems to indicate even in pipelined interfaces the waitrequest signal is still the key signal used... And it's that signal that's currently only allowing me one read/write per access.. (e.g. waitrequest is asserted immediately after my first request and I can't issue another request until the waitrequest signal is deasserted.) 


If anybody could enlighten me on using pipelined accesses with the [free] Altera SDR SDRAM controller core, I'd greatly appreciate it ... 


Lastly -- if pipelined transfers are supported, it seems (highlighted text in above quote) that only pipelined READS are supported, but pipelined writes are not ... is that also a correct understanding? 






ps.- within the FPGA, I'm only attaching to the following SDR SDRAM core signals: 

address, chipselect, read, readdata, waitrequest, write, writedata, byteenable
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Honored Contributor II

Yes, the pipelined transfers are supported, read and write. 


Just write simple Avalon Master, which writes or reads permanently (do not forget the incrementintg the address (+4) while waitrequest is low) and see what happens in simulation :-) It should work perfectly.