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Does SDR SDRAM controller have pin restrictions?

Altera_Forum
Honored Contributor II
824 Views

Hello. 

 

I'm using the Altera Single Data Rate SDRAM controller for a NIOS2 Cyclone4E design. 

 

Does the SDR SDRAM controller have any pin restrictions like the DDR controllers have, or can I assign any general IO pin to the DQ signals of the SDRAM? 

 

Thank you 

Scott Wild
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
99 Views

The SDR SDRAM standard use 3.3V LVTTL signalling.

Altera_Forum
Honored Contributor II
99 Views

in my knowledge, you can assign DQ pins and other pins to any location (except the pins which only have input ability). 

 

good way to confirm those things is to create QuartusII project for your schematic as TEST. 

if the location is incorrect then QuartusII gives you errors.
Altera_Forum
Honored Contributor II
99 Views

Thank you for the advice. 

 

Scott.
Altera_Forum
Honored Contributor II
99 Views

The only thing I did take care of was the SDRAM clock output. As this usually connects directly to a PLL, you should use the dedicated input and output pins for the PLL you select. 

My Quartus had problems deciding where to put the PLL, so I had to manually assign it to PLL2 (Cyclone3, Quartus 9.1SP2).
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