FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Does a slow Avalon slave block the Lightweigh HPS-to-FPGA bridge?


We have multiple Avalon slave devices running off the Lightweight bridge on a Cyclone V. One device is fairly slow and has to do long block transfers (32 bit transfers at a time). The IP holds waitrequest active for most of the cycle releasing it just at the end so the next request can come in. I'm not clear - while each word is being transferred is the lightweight bridge able to service requests to other slaves while it's waiting for the slow slave to complete its transfer or will other accesses stall until the transfer completes?

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The H2F lightweight bridge can support single and multiple transaction/s. There is a master unit called Global Programmer's View (GPV) which controls the interface bridges. The GPV allows you to set the bridge’s issuing capabilities to support single or multiple transactions. The GPV also lets you set a write tidemark through the wr_tidemark register, to control how much data is buffered in the bridge before data is written to slaves in the FPGA fabric. 

You can refer to this document :



page (9-35)


Thank you