Does the Intel FPGA Avalon I2C (Master) Core issue a STOP after receiving a NACK? If not, how can just a STOP be issued without transmitiing any data.

[Isaac_V_Intel]

Hello Bill.

I'm seeing at the link [1] that you get a NACK or Stop condition after transfer data.

Could you please elaborate more what you need. The guide of the Avalon I2C below for more information.

[1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf#page=175

Best regards.

Isaac

[BAdam1]

If the I2C Master Core gets a NACK when the device address is transmitted, how does it behave? Does it just set the MAK bit in the ISR? Does it issue a STOP? Does the driver need to issue the STOP or a repeated START?

[Isaac_V_Intel]

Hi Bill,

If you follow the link [1] drives you to page 178 with some examples of transmitting or receiving data.

Also, you can see more information about the protocol, specifically NACK on the link [2] on page 5.

[1]https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf#page=178

[2] http://www.ti.com/lit/an/slva704/slva704.pdf

[Isaac_V_Intel]

Hi Bill,

Did the information works for you to understanding your issue?

Best regards,

Isaac.