Dual speed uart

[Altera_Forum]

Hi all,do you know if exist some uart ip with dual speed setting - the first setting speed for TX Uart and the second setting speed for RX UART ?We need send the data from NIOS quickly and read data from serial bus slowly. (In microcontrollers like x51 from Silabs or Atmel uarts have these settings.)I havent found yet any uart ip with this option.Thank you for your answer.Jan Naceradsky, Czech Republic

[Altera_Forum]

You can simply use two uart controllers, the first for tx only and the second for rx only. 

If the rx part on the first one and the tx part on the other are left unconnected, I believe the synthesis tool  would remove most of unused logic and you won't have major resource waste compared to a solution with a dual-speed ip.

[Altera_Forum]

Good idea! 

But it doesnt work, how we think. I use fifoed avalon uart and when i connect rx and tx to uart, it takes about 480LEs. When i disconnect rx or tx from uart, it takes about 470-480LEs, too. When i dont use fifo for tx or rx in settings in QSYS, it takes about 370-380LEs. But it is only about 100LEs fewer than all connect uart. Why so few ?

[Altera_Forum]

This makes sense. 

If you configure fifoed rx, the fifo would be implemented even if rx input line is not connected, since fifo can still be accesses from avalon MM slave port; that's why you must explicitly disable it. Please note that a fixed resource cost is due to the uart clock and the synchronization with Avalon slave clock and I believe this accounts for a great part of those LEs. So I expect the total resource usage would have been similar even with a double speed uart, since this clock related part had to be replicated for rx and tx clocks. The real wasted resource are those needed to implement registers available on the slave port which are no more used (i.e. rx register on tx part); they cannot be optimized away since you can still rd/wr them.  For example let's suppose that a complete uart requires 500LE, divided this way:  uart clock control and synchronization: 200LE  rx stage : 150LE  tx stage: 50LE  decoder and registers: 100LE With a dual speed ip you'd have to replicate the first block, so you'd get a total 700LE With two single speed uarts, you spare 1 rx and 1tx stage and you need a total of 800LE  Clearly, the benefit of a single dual speed ip depends on the actual resource division, which I don't know