Dynamic Reconfiguration and Clock problems

[Altera_Forum]

Hi, 

 I've tried compiling the altera's reference design for dynamic reconfiguration and it compiles perfectly. In the design there are 4 gxb each with 2 refclock and one reconfig module. However, when I implemented the same thing in my design, quartus says that it can't fit the design since it's only allowed to have 8 global signals into quad. It seems that in the reference design the reconfig_clk pin is left unassigned which quartus then assigns one to it during compilation, but that's not possible in a real design. Anyone got any ideas on how to fix 4gxb with 2 refclock with dynamic reconfiguration into one quad?  Thank you in advance

[Altera_Forum]

So you are actually using both refclk pin pairs into the quad? That is slightly different from my designs. I have several designs that use two reference clocks, all 4 GXB in a quad with TX and RX, and dynamic reconfiguration. However, I also ran into the problem of not having enough global clocks to support all of the clock signals. What I did was use the assignment editor to tell Quartus NOT to put the recovered clock from the receiver on a global route. 

 e.g. set_instance_assignment -name GLOBAL_SIGNAL OFF -to *rx_clkout_wire*   Jake

[Altera_Forum]

Thanks Jake! It works!