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SSikk
Beginner
198 Views

E-Tile Hard IP for Ethernet Intel FPGA IP in Quartus 19.3 tool for Stratix 10-DX Device

Our design is integrated with P-Tile PCIe with Ethernet of Datawidth 512bits. Ethernet link is up but o_tx_ready of ethernet is toggling all the time rather than being high or low for some time. .stp file is attached for reference.

 

Can anyone please update me the reason for this?

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4 Replies
Deshi_Intel
Moderator
71 Views

HI,

 

It's not easy to isolate issue when your design is complex and combined both PCIe and Ethernet IP together.

 

My advice is perhaps you can try out new design with just Ethernet example design only. Make sure everything works first (both Quartus design and your board) then only add in PCIe design to it.

 

Thanks.

 

Regards,

dlim

SSikk
Beginner
71 Views

Hi,

Thanks for your support.

 

We tested example design thrice. tx_ready is behaving in the same way what I mentioned in my previous post.

 

Can you please guide us on how to isolate this issue?

 

Deshi_Intel
Moderator
71 Views

HI,

 

Thanks. I have reviewed your signal_tap result. Below is my comment.

 

As I mentioned before, there could be 3 possibility that maybe impacting the Ethernet IP behaviour and we can rule them out one by one

  1. Potential Quartus design issue
  1. Potential S10 device itself issue or board design or power up issue

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
71 Views

HI,

 

I don't hear back from you after my feedback suggestion.

 

Hopefully you are able to make good progress with your project development

 

For now, I am setting this case to closure.

 

Thanks.

 

Regards,

dlim

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