EMIF Cyclone 10 GX: emif_usr_clk frequency incorrect

[Schroeti]

Hi,

i've instantiated the EMIF IP core to connect to a DDR3 SODIMM memory on a customer board. The EMIF is fed by a configurable clock generator. Some information:

- pll_ref_clk frequency: 100MHz

- memory clock frequency: 800MHz

- clock rate of user logic: quarter

- Quartus prime pro; version 20.3

Everything works fine, except one thing:
The timing analyzer reports a emif_usr_clk frequency of 100MHz while this is actually 200MHz (measured with oscilloscope).

Then I compiled the design with different pll_ref_clk settings with following reported results:
pll_ref_clk frequency - usr_clk frequency
50MHz - 200MHz
100MHz - 100MHz
200MHz - 50MHz

Strange. My understanding is, that the user clock only depends on the memory clock.

I'm afraid this wrong frequency affects synthesis and fitting results badly.
How can i fix this?

[yoichiK_intel]

Hi

If your memory clock is 800Mhz and quarter rate for user logic is chosen emif_usr_clk frequency should be 200Mhz.

Can you attach your QAR design in this forum ?

[Schroeti]

Here it is.

[yoichiK_intel]

Hi 

When I compile the design I see the emif_usr_clk is reported as 200Mhz in the clocks GUI. Can you confirm ?

[Schroeti]

Yes, exactly as I logged. Sorry, I forgot to change the reference clock back away from 50MHz before generating the qar.

Would you please set the emif pll reference clock to 200MHz, then you should see the effect.

[yoichiK_intel · Accepted solution]

In the top.sdc you are setting pll reference clock as 50Mhz and this causes the incorrect emif_usr_clk frequency.  Please remove the following constraint from sdc then you should see the correct clock frequency in the report.   The pll reference clock frequency is defined in the IP sdc.

create_clock -name {clk_emif} -period 20.0 [get_ports {emif_clk_clk}]

[Schroeti]

That's it.

Thank you!