FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5952 Discussions

Embedded memory Mem Init questions

HKim27
New Contributor I
562 Views

I have questions for options in "Mem Init" tab in "RAM: 1-PORT" IP.

 

1.

According to the document, if I select "No, leave it blank", the memory initializes to zero. Is it mean power-up initialization? Is it initialized when partial reconfiguration applied, too?

 

2.

There is "Implement clock-enable circuitry for use in a partial reconfiguration region" which adds "freeze" input to RAM. I think that RAM contents does not change while freeze == 1.

But how is this possible? During partial reconfiguration, wire to RAM's freeze input is also rewired, so we cannot determine the value of freeze input.

 

Thanks in advance.

0 Kudos
1 Reply
sstrell
Honored Contributor III
124 Views

I'm assuming you are targeting a device that supports "current" PR (Cyclone 10 GX, Arria 10, Stratix 10) and that you are using the Pro edition of Quartus.

 

1) Yes, on-chip memory should initialize like other registers on power-up without initialization: all 0's. However, if you want to guarantee this, you should add memory reset code to your design to blank out the RAM (a for loop that runs on reset).

 

2) No. The freeze signal is generated in the static region (normally by the region controller IP) so it is always correct. And the freeze signal only feeds logic in the static region, not the PR region. The option you mention (which I had not seen before) is meant for initialized RAM that is put in the PR region to prevent issues with the initialization of the contents of that RAM, not in the static region. Check out page 22 of the PR user guide for the circuit I'm guessing this option is implementing: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-pr.pdf

 

#iwork4intel

Reply