Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constr

[Murali_kumar]

Hi all,

I have implemented the "e tile hard ip" single channel 10g ethernet
interface in statix10tx device.
The pin assignments are taken care as follows,

reconfig clock
--------------------
ref_clk_p Input PIN_BA35 2A LVDS
ref_clk_n Input PIN_AY35 2A LVDS

transceiver ref clock
--------------------
e1_g1_clk_p Input PIN_AC41 8C Differential LVPECL
e1_g1_clk_n Input PIN_AD40 8C Differential LVPECL

transceiver lines
--------------------
e1_g1_ch1_txp[0] Output PIN_AD49 8C High Speed Differential I/O
e1_g1_ch1_txn[0] Output PIN_AD48 8C High Speed Differential I/O
e1_g1_ch1_rxp[0] Input PIN_AD43 8C High Speed Differential I/O
e1_g1_ch1_rxn[0] Input PIN_AD42 8C High Speed Differential I/O

The same pins were verified with 1st280 pin details sheet also.

but during the fitter stage i am facing the following error,

=============================
Error(14566): The Fitter cannot place 1 periphery component(s) due to
conflicts with existing constraints (1
HSSI_C3_DUPLEX_CHANNEL_CLUSTER(s)). Fix the errors described in the
submessages, and then rerun the Fitter. The Intel FPGA Knowledge
Database may also contain articles with information on how to resolve
this periphery placement failure. Review the errors and then visit the
Knowledge Database at
https://www.altera.com/support/support-resources/knowledge-base/search.html
and search for this specific error message number.
Error(175020): The Fitter cannot place logic
HSSI_C3_DUPLEX_CHANNEL_CLUSTER in region (1, 289) to (11, 359), to which
it is constrained, because there are no valid locations in the region
for logic of this type.
Error(16234): No legal location could be found out of 1
considered location(s). Reasons why each location could not be used are
summarized below:
Error(20196): Location(s) already occupied and the
components cannot be merged. (1 location affected)
Error(15307): Cannot apply project assignments to the design due to
illegal or conflicting assignments. Refer to the other messages for
corrective action.
Error(16297): An error has occurred while trying to initialize the plan
stage.
Error: Quartus Prime Fitter was unsuccessful. 6 errors, 0 warnings
Error: Peak virtual memory: 14660 megabytes
Error: Processing ended: Tue Oct 12 11:18:39 2021
Error: Elapsed time: 00:06:39
Error: System process ID: 2060
Error(175020): The Fitter cannot place logic
HSSI_C3_DUPLEX_CHANNEL_CLUSTER in region (1, 289) to (11, 359), to which
it is constrained, because there are no valid locations in the region
for logic of this type.
Error(16234): No legal location could be found out of 1 considered
location(s). Reasons why each location could not be used are summarized
below:
Error(20196): Location(s) already occupied and the components
cannot be merged. (1 location affected)
Error(16234): No legal location could be found out of 1 considered
location(s). Reasons why each location could not be used are summarized
below:
Error(20196): Location(s) already occupied and the components
cannot be merged. (1 location affected)
Error(20196): Location(s) already occupied and the components cannot be
merged. (1 location affected)
Error: Peak virtual memory: 14660 megabytes
Error: Processing ended: Tue Oct 12 11:18:39 2021
Error: Elapsed time: 00:06:39
Error: System process ID: 2060
==============================
please let me know, if anybody have any idea about this...

Regards
Murali kumar

[Murali_kumar · Accepted solution]

Issue solved, problem in pin assignment name in inside logic

[Deshi_Intel]

HI,

Looks like you maybe facing E-tile pin placement issue as E-tile hard IP has its own dedicated pin placement rule

Have you tried out the E-tile channel placement tool as shown in E-tile Hard IP user guide doc page 326, chapter 4.1 ?

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug20160.pdf

The tool will help to validate to ensure you are using the correct and valid pin location.

Thanks.

Regards,

dlim

[Murali_kumar]

Yes it was solved and thanks for your effort.

[Deshi_Intel]

Welcome !