Today I am building a DDR4 project using the Arria10 EMIF Interface. When I configured the project for DDR4-2400R LRDIMM x72, I generated an example that contains two traffic generators, two Arria10 EMIF Interfaces, although I specified 1 DIMM in the settings. This is my first project with DDR4, so I connected the second LRDIMM to the emif_1_slave module.
When compiling, fitter indicates errors:
Error (14566): The Fitter cannot place 2 periphery component (s) due to conflicts with existing constraints (1 OCT calibration block (s), 1 REFCLK_GROUP (s)).
Error (175020): The Fitter cannot place logic OCT calibration block that is part of Arria 10 External Memory Interfaces ed_synth_altera_emif_180_kgljw4i in region (78, 168) to (78, 171), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component (s):
Info (175 028): The OCT calibration block name (s): ed_synth: ddr4_lrdimm | ed_synth_altera_emif_180_kgljw4i: emif_0 | ed_synth_altera_emif_arch_nf_180_r4boqsy: arch | ed_synth_altera_emif_arch_nf_180_r4boqsy_top: arch_inst | altera_emif_arch_nf_oct: oct_inst | cal_oct.powerup_oct_cal.termination_inst
Error (16234): No legal location could be found out of 1 considered location (s). Reasons why each location could not be used are summarized below:
Info (175015): The I / O pad ddr4A_oct_rzq_i is constrained to the location PIN_F25 due to: User Location Constraints (PIN_F25)
Info (14709): The constrained I / O pad is contained within a pin, which is contained within this OCT calibration block
Error (175006): Could not find path between the OCT calibration block and destination pin
Info (175027): Destination: pin ddr4B_ba_o 
Info (175015): The I / O pad ddr4B_ba_o  is constrained to the location PIN_N9 due to: User Location Constraints (PIN_N9)
Info (14709): The constrained I / O pad is contained within this pin
Error (175022): The OCT calibration block could not be placed in any location to satisfy its connectivity requirements
Info (175021): The pin was placed in location N9
Info (175029): 1 location affected
Info (175029): TERMINATION_X78_Y168_N6
Please help me remove the error and understand why Quartus generated two traffic generators and two EMIF cores
The easiest answer is that probably the IP parameter editor was not set up correctly. Can you share your EMIF parameter editor settings that led to the generation of this example design?