Error 20445 in Tri Speed Ethernet IP for Stratix 10

[GIFT]

Error(20445): The reference clock on PLL "ethernet_1g_top_inst|tx_side_ethernet_1g_inst|ethernet_multi_rate_ip_inst|eth_tse_0|i_lvdsio_0|core|arch_inst|pll_inst|internal_pll|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", which feeds an LVDS SERDES IP instance, is not driven by a clock pin from an IO bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

I am using two instances of the same IP. But I have been receiving the same error on one of the instances. IP is used for unidirectional mode. For one instance only TX is used and in the other instance, only Rx is used.  We got the above error in the Rx side instance. 

I have checked the bank and the pin connections. Everything is properly connected. 

Kindly help me to solve this issue

[Deshi_Intel]

Hi,

There are 2 possibility that I can think of.

1. You didn't assign the refclk pin to use "dedicated refclk" pin as indicated in the error message
2. Did you assign the 2 TSE IP instance into same IO bank ?

• This will caused the error as stated in page 170, chapter 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
  • You need to split them into different IO bank

Thanks.

Regards,

dlim