Error(332000)

[ymiler]

Hi

I get error messge in the plan process (attached)

Can you advice how can I fix it ?

Yishay

Error(332000): ERROR: Quartus Prime Tcl command "get_atom_node_info" belongs to the "::quartus::atoms" package which is currently not loaded. Please type "load_package atoms" to load the package before using this command.

while executing
"get_atom_node_info -key TYPE -node $cell_id"
(procedure "altera_iosubsystem_node_is_type" line 12)
invoked from within
"altera_iosubsystem_node_is_type $node $atom_type"
(procedure "altera_iosubsystem_search_back_from_node_to_atom" line 3)
invoked from within
"altera_iosubsystem_search_back_from_node_to_atom $node $atom_type $search_iter"
(procedure "altera_iosubsystem_get_atom_by_lvds_input" line 9)
invoked from within
"altera_iosubsystem_get_atom_by_lvds_input $lvds_core_instance_name $is_tx_outclock $atom_type $search_iter "fclk""
(procedure "altera_iosubsystem_get_iopll_atom" line 5)
invoked from within
"altera_iosubsystem_get_iopll_atom $lvds_core_instance_name $lvds_search_mode "
("foreach" body line 12)
invoked from within
"foreach lvds_instance_name $lvds_instance_name_list {

[sstrell]

Can you describe what you were doing to get this error?  Is it repeatable?

[ymiler]

Yes ,

Its repeatable - I am stuck , I can't generate FPGA version 

My change was  defintion on  the LVDS SERDES IP GUI  -  get clock from external PLL instead of internal PLL

Yishay

[sstrell]

So you're trying to (re)generate the IP in the IP Parameter Editor?  Need to be more specific of exactly what you are doing and when the error occurs.

Can you show a screenshot?  Are there any errors in the messages at the bottom of the IP Parameter Editor before you generate the IP, possibly indicating that you have incompatible parameters selected?

Can you try creating a brand new instance of the IP to see if the error still occurs?

And what is your Quartus version and target device?

Lots of basic info needed here to figure out what's going on.

[ymiler]

Hi

The error occure in the middle of plan stage 

Attach screenshot :

Quartos version 20.3

My target device : 

I have the LVDS SERDES IP in my project -My change was  defintion in the IP GUI to   get clock from external PLL instead of internal PLL

There are no errors/warnings in the GUI editor when I try to regenerae 

Attached screenshot :

BR

Yishay

[ymiler]

And one more thing ,

If I comment the instance (in the code) - the error doesn't occur

[ymiler]

Wired , 

I generate new IP  - like the older ( same parameters ) but new one 

Then , I replaced the instance in my project and everything was good - I succseed to generate FPGA sof file 

I didn't understand  the problem because the Quartos error message was not clear

Yishay

[AminT_Intel]

Hello,

Which version of Quartus are you using? Have you tried to load the package as suggested in that error?

Thanks.

[ymiler]

Hi

I tried to load the package by the TCL console but nothing changed

My Quartus version is 20.3  

[Timothy_W_Intel]

The issue is the order of the .ip files. The pll.ip needs to be before the lvds_serdes.ip in the qsf file.

See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-lvds.pdf#page=53

[AminT_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[TW_fpga]

an updated link

https://www.intel.com/content/www/us/en/docs/programmable/683792/21-2-20-0-0/timing-analysis-for-the-external-pll-mode.html