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Altera_Forum
Honored Contributor I
2,277 Views

Error: WYSIWYG RAM primitive "ram_block1a0" must have Port A, Data In port or paramet

I've got this error after generating SOPC system. 

 

 

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Error: WYSIWYG RAM primitive "ram_block1a0" must have Port A, Data In port or parameter specified 

 

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The error points to the file generated by Quartus, I attached.  

Anyone got the same problem? 

Thanks :)
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8 Replies
Altera_Forum
Honored Contributor I
509 Views

Problem solved by grounding reconfig_clk

Altera_Forum
Honored Contributor I
509 Views

Hi all, 

I have the same error but I don't understand what I have to do to resolve it. 

 

Anyone can help me ? 

 

thank you
Altera_Forum
Honored Contributor I
509 Views

This error usually means that an input port on a ram block is not connected correctly. The error info is atrocious. 

1. If you have more than 1 ram block, delete all but 1, maybe just Gen Functional net list to check for error, (Should be quicker than compile, either should work) 

2. Look very carefully at the input connections. For instance not having an enable connected will generate an error for every data inut. 

Good Luck All!
Altera_Forum
Honored Contributor I
509 Views

Correct, last time I left some pins float. it's not used actually but you have to ground them properly.

Altera_Forum
Honored Contributor I
509 Views

I think I found it. 

 

I changed the name of an input pin port which feeds the data port of an lpm_fifo, but I forgot to change the name on the fifo's wire. 

 

I should have the error "input port of# ## has no driver" instead of the error with the WYSIWYG RAM but I haven't. 

 

What I have done to find the error is to force the fifo to be made only with Logic Element. With this parameter, I have the good error "input port of# ## has no driver". When this is corrected, I can compile my project with fifo made with either LE or M9K. 

 

strange behavior of quartus.... 

 

 

for info : the fifo is in a sub "bdf file".
Altera_Forum
Honored Contributor I
509 Views

hi, 

 

I had the same problem after I changed the clock domain. then I found out that I didn't connect the new clock to the module. after connecting that, the problem solved. generally this error causes when you didn't connect the clock signals properly. 

 

thanks, 

Aidin.
Altera_Forum
Honored Contributor I
509 Views

if you use multiple RAM s in your project, dont name busses and pins like this ramaddress1 ramaddress2 ramaddress3 because quartus thinks its the same busses with different something i dont know what it really thinks but it will generate the error you typed in this thread. use names like ramaddressA ramaddressB ramaddressC. that saved my 3day fight with theis unseen misterious error iv chased... and all because of the numbers in the pin names. actually verilog will also have serious problems making differense between myaddress1 and myaddress2. instead use myaddress_one myaddress_two.

Altera_Forum
Honored Contributor I
509 Views

 

--- Quote Start ---  

if you use multiple RAM s in your project, dont name busses and pins like this ramaddress1 ramaddress2 ramaddress3 because quartus thinks its the same busses with different something i dont know what it really thinks but it will generate the error you typed in this thread. use names like ramaddressA ramaddressB ramaddressC. that saved my 3day fight with theis unseen misterious error iv chased... and all because of the numbers in the pin names. actually verilog will also have serious problems making differense between myaddress1 and myaddress2. instead use myaddress_one myaddress_two. 

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Same here but replacing digits 1,2...3 with A,B...C did not make any difference. :(
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