Hi all, I'm having some problems when compiling my design with Altera DSP Builder (my current version is v16.1 and MATLAB R2016a). It has been for months since I started building my projects with Altera DSP Builder software and compiling the HDL design by using the SignalCompiler blockset. Everything has worked fine until today. This morning when I compiled my simulink design as usual, the SignalCompiler window shows me an error while analyzing model:
Could anyone show me how to fix this error ? Thanks.
Update: I found the errors in the Avalon-MM Slave block, which happened to miss the connected wire to the read data signal. This block is appeared to be automatically disconnect the already-connected wire occasionally and I don't know why.
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