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Error running emi_ddr2_aiigx with Q10.0sp1 on Dev. Kit Arria II GX EP2AGX125EF35

Altera_Forum
Honored Contributor II
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I compile/refresh EMI DDR2 Ref. Design (DDR2: Interfacing a 267-MHz DDR2 SDRAM with an Arria II GX FPGA, i can't put the link) with Q9.1sp2 and work ok on my Arria II GX FPGA Development Kit. 

But, when I open design with Q10.0sp1 and refresh DDR2 core, the design is not running. I use SignalTap to monitor „test_complete” signal but this never get value of ’1’, like on Q9.1 version. 

I have to import the core or someting like that? (I am a beginner with Altera) 

Thanks, 

Regards.
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