Honored Contributor II
06-08-2011 06:22 PM
I compile/refresh EMI DDR2 Ref. Design (DDR2: Interfacing a 267-MHz DDR2 SDRAM with an Arria II GX FPGA, i can't put the link) with Q9.1sp2 and work ok on my Arria II GX FPGA Development Kit.But, when I open design with Q10.0sp1 and refresh DDR2 core, the design is not running. I use SignalTap to monitor „test_complete” signal but this never get value of ’1’, like on Q9.1 version. I have to import the core or someting like that? (I am a beginner with Altera) Thanks, Regards.