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Error while generating DDR2 IP core for CycloneIV in Quartus13.1

Altera_Forum
Honored Contributor II
‎10-07-2014 05:40 AM
1,054 Views

Hi all, 

Can anybody help me out to remove the following error I am getting while generating the core. 

---------- 

Error (332000): can't read "dqsclksource": no such variable 

while executing 

"create_generated_clock -multiply_by 1 -source $dqsclksource -master_clock $dqsclksource $dqspin -name $dqs_out_clockname -add" 

(procedure "add_requirements_for_instance" line 263) 

invoked from within 

"add_requirements_for_instance $corename $inst t board ISI $DDR2_USB_phy_use_flexible_timing" 

("foreach" body line 3) 

invoked from within 

"foreach inst $instance_list { 

post_sdc_message info "Adding SDC requirements for $corename instance $inst" 

add_requirements_for_instance $corename $..." 

(file "DDR2_USB_phy_ddr_timing.sdc" line 635) 

---------- 

 

If I comment those lines in .sdc file, I am getting similar errors for other variables. 

 

Thanks in advance.
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