When I use the MAX 10 Single-Port TSE reference design. I encounter some problems. I use version 18.0 of the reference design in Quartus 18.0. First of all when I open the design in platform designer only the Triple-Speed Ethernet IP is recognized. For the other components such as the Ethernet Packet Monitor and the Ethernet Packet Generator I get an error saying: component could not be found or instantiated.
I could only replace the Avalon-ST Multiplexer, Avalon-ST Splitter and the Error adapter. In my current design I have left out the Packet Generator and Packet Monitor and exported one source of the Splitter and one sink of the Multiplexer.
But when I run the test (TEST_ST_LB 1000M) now with the external packet generator the statistic counter of the TSE MAC gives for aFramesTransmittedOK = 406491076
aFramesReceivedOK = 0
My goal is to monitor the incoming and outgoing Ethernet packets of the TSE MAC so later on I can export the source and the sink of the TSE MAC to the HSMC pins of my MAX10 FPGA.
Could any one help me out? How can I get this working with the tcl scripts of the reference design?
Any help would be appreciated.
I believed you are referring to TSE reference design in below link.
As you can see, the reference design is developed and validated in Quartus v16.0. My recommendation is to try to bring up the board and test everything in v16.0 first as v18.0 is not validated. We don't support reference design migration
Thanks for your quick reply.
Now the statistic counters in the System Console give the right amount of received and transmitted Ethernet packets.
But the packets dont show up on the receiving Ethernet port in Wireshark. Do you know why and how I could receive them there?
I configure Both FPGA's with the same tcl script.
Yes it's still about the "Avalon-ST reverse Loopback Test" TEST_ST_LB 1000M.
I already tried to view the TX channel and RX channel signals on a scope, by measuring on the HSMC pins of the MAX 10 Development kit.
But I couldn't see any of the signals except for the FIFO RX and TX clocks. On the other pins I only detected noise.
This was the case when I used the "Standard Differential Host Pinout" of the HSMC Specification. But I geuss only the "Standard Single-Ended Host Pinout" is supported by the MAX 10 Development kit.
But now that I am trying to map the Avalon-ST signals of the TSE MAC according the Single-Ended Host Pinout I discovered that not all pin mapping is documented in the MAX 10 User Guide.
Could you confirm which Pinout I should use for the MAX 10 Development kit?
Looks like you are running test using your own TSE design instead of the "MAX10_TSE_On-board_PHY_Design_Example" (max10tse_q_16_0_project) as example design TSE is connected to on board Marvell 88E1111 PHY chip, and not to HSMC connector.
For question on supported IO standard on HSMC connector
For question on supported IO standard on Avalon-ST signal
When using the single ended IO standard there is only a mapping of the first 16 data pin pairs of the HSMC connector of the MAX 10 Development kit and the HSMC card.
And additionally 2 extra data pin pairs D0, D1, D2 and D3.
Now I'm missing 6 data pin pairs for the Avalon-ST.
But I can't find the pin Mapping for the other data pins described in the HSMC Specification. For example D8 (pin 53) or D10 pin 55.
Is there an additional Pin mapping of the MAX 10 HSMC pins available or are these data pins limited by the 18 data pin pairs that I am using now?
Yea there is more than 18 data pins, but the Mapping with the HSMC specifications isn't right.
But I have already solved it by using the schematic of the MAX 10 development kit for the pin mapping.
I have another issue with my design. Now I am able to see the Avalon-ST signals which I mapped to the top level file top.v on my scope. But these signals do not appear as I expected (square waves) but more like sine waves.
I think that the risetime of the clock signal is not met which causes a sine wave instead of a square wave.
So I tried to test the Reference design in 100Mbit mode instead of 1000Mbit mode. But I can't seem to get the design in 100Mbit mode.
My question is: do I need to change the clock speed in the top.v file, by replacing enet_tx_125 with enet_tx_25 as clock parameter for the TSE MAC
Or can I change the clock speed through the System Console with the tcl script?
in the attachment you can see in orange the clock (enet_tx_125) which is way smaller than I expected. The green line is rx_dval, yellow line is rx_data and purple is rx_data.
As you can see the data is not a squarewave as in my simulation.
Pls see my reply below.