FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

External Memory

Altera_Forum
Honored Contributor II
1,138 Views

Can some one explain how to generate memory designs, allocate pins for the design and generate programming file for the design. I want the complete set of QSF file with design files. And also I want to know that whether I can add my own QSF to the design and compile it. 

 

Reply ASAP..........
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
288 Views

Write the memory contents in .mif file format. 

Allocate pins using the pin planner. 

Use Quartus II to generate programming files. 

To archive the complete set of source files, use the "archive" command in the QII menus. 

No you can not add a .qsf to the project, each project IS a single .qsf file, but you can merge two .qsf files into a single one. 

 

To get ASAP answers read the manuals.
0 Kudos
Altera_Forum
Honored Contributor II
288 Views

Thanks for the feed back, 

 

I went through the manuals and I am able to generate design now. But one thing I want to confirm is for memory part MT47H32M16-5E the address width in the top level file(variation file) is set to 16 i.e. (15:0) but according to data sheet of the part it should be 13 (12:0). Can you get back on this why it is different from data sheet. 

 

thanks in advance.
0 Kudos
Altera_Forum
Honored Contributor II
288 Views

You set the address width in the IP gui.

0 Kudos
Altera_Forum
Honored Contributor II
288 Views

But that creates a custom part right? 

Can you tell me what's the reason behind setting the address width to a value that is not specified by a memory data sheet.
0 Kudos
Altera_Forum
Honored Contributor II
288 Views

It may, I am not sure, but your address width depends on how you are using your memory, is it a DIMM or just a single component for example?

0 Kudos
Altera_Forum
Honored Contributor II
288 Views

its a component.

0 Kudos
Reply