F2Sdram Arria10 configuration

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

F2Sdram Arria10 configuration

1,182 Views

Hello,

For a project on an Arria 10 (10AS066H3F34I2SG), i need 2 F2Sdram ports with different data widths.

BUT when i chose configuration 4 (f2sdram0 -> 128bits, f2sdram1 -> 32bits, f2sdram2 -> 64bits), all data widths are fixed to 128bits.

Are there a fix to this issue?

ps: Quartus version: Prime SE build 211.

Thanks

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.