F2Sdram Arria10 configuration

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

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Hello,

For a project on an Arria 10 (10AS066H3F34I2SG), i need 2 F2Sdram ports with different data widths.

BUT when i chose configuration 4 (f2sdram0 -> 128bits, f2sdram1 -> 32bits, f2sdram2 -> 64bits), all data widths are fixed to 128bits.

Are there a fix to this issue?

ps: Quartus version: Prime SE build 211.

Thanks

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