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FFT 8.0, sink_ready de-asserted

Altera_Forum
Honored Contributor II
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Hi, 

 

I am trying to test the functionality of FFT version 8.0. The device family that I am using is Cyclone II. Below is the parameter of the FFT: 

 

Transform Length: 64 points 

Data Precision: 8 bits 

Twiddle Precision: 8 bits 

I/O Data Flow: Streaming 

Structure: 4 Mults/2Adders 

Implement Multipliers in: DSP Blocks/Logic Cells 

Twiddle ROM Distribution 100% M4K 

 

As for the FFT input, I wrote a FSM code for it. My input looks fine, sink_sop, sink_eop and sink_valid are where it is suppose to be. However sink_ready was asserted at the beginning, one clock cycle before sink_valid and sink_sop were asserted. Then sink_ready was de-asserted half way before sink_eop (before 64 data ends). As a result, source_error shows “11”; meaning that EOP is asserted before 64 valid samples are accepted.  

 

Since I am using streaming architecture, I thought this architecture allows continuous processing of input data and outputs a continuous complex data stream. So that means the sink_ready was suppose to be asserted all the time isn’t it? Unlike in buffered burst and burst architecture, sink_ready signal will be de-asserted when FIFO is filled. So why for streaming architecture in my case, the sink_ready can be de-asserted causing it unable to accept data? Does anyone know this answer?
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Altera_Forum
Honored Contributor II
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Hi thepancake, thanks for everything. I couldn't use Modelsim , cause the software is not included with the Quartus II Web Edition. But I will try to find other way to solve this. Hopefully...

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Altera_Forum
Honored Contributor II
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there's a web edition of ModelSim too. 

 

http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html 

 

but in the second waveform i posted i just used the graphical testbench editor and Quartus simulator and got the correct results.
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Altera_Forum
Honored Contributor II
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Hi, 

I got good news, for the problem (sink_valid goes low half way during input) the mistake was I did not turn on Global Clock Enable during code generation. The pin "clk_ena" needs to be there and set high for it to work properly, other wise there will be a warning like this: 

 

Can't find signal in vector source file for input pin "l fft_test1 l fftblock: inst l asj_fft_sglstream_fft_81 : asj_fft_sglstream_fft_81_inst l clk_ena"
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Altera_Forum
Honored Contributor II
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Hi bellman, 

 

would it be possible, that you upload your project-files? I am a bloody beginner and would like to see how you build up such a FFT. 

 

That would be great :) 

 

Regards, 

LarsD
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Altera_Forum
Honored Contributor II
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hey bellman, 

 

sorry i didn't get back to you, i've been swamped at work. glad you got it working and thanks for posting the solution.
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Altera_Forum
Honored Contributor II
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Hi LarsD,  

I could only post it to you few days later.. hope you could wait a little longer.. By the way, I had a little problem cause I am trying to compare my input (after goes through IFFT and FFT) and output to see if I could get back the original data. (I think it is called Unity Gain). Still trying to figure out, I think there is some operation such as scaling and 1/N multiplication involve. Get back to you soon.
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Altera_Forum
Honored Contributor II
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Hi bellman, 

 

I just get it ;) But thanks for your help!
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Altera_Forum
Honored Contributor II
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hey bellman, 

 

there is some Verilog in the Altera design example that should help you figure out the unity gain stuff. 

 

http://www.altera.com/support/examples/verilog/ver-cascaded-fft-ifft.html
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Altera_Forum
Honored Contributor II
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i was able to modify the unity design example to work in Quartus 8.1 (i think the original design was 16-bit data/twiddle and streaming so that's what i used). the design example is basically taken from AN404. 

 

http://www.altera.com/literature/an/an404.pdf
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Altera_Forum
Honored Contributor II
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Hi, 

 

Sorry to keep you waiting LarsD. 

 

I am still investigating on unity gain. The input to the IFFT block initially starts with FSM that generates 64 symbols (N = 64), 4 bits each symbol. Because IFFT block requires 8 bits, real and imaginary data, I use another block to mapped it to fit the requirement. The mapping it such as shown below: 

 

0000 ---> -96 - j96 

0001 ---> -96 - j32 

0010 ---> -96 + j96 

0011 ---> -96 + j32 

0100 ---> -32 - j96 

0101 ---> -32 - j32 

0110 ---> -32 + j96 

0111 ---> -32 + j32 

1000 ---> 96 - j96 

1001 ---> 96 - j32 

1010 ---> 96 + j96 

1011 ---> 96 + j32 

1100 ---> 32 - j96 

1101 ---> 32 - j32 

1110 ---> 32 + j96 

1111 ---> 32 + j32 

 

Negative numbers represented in second compliment. Then the output from IFFT is connected directly to FFT. After that, in order to do scaling, I created another block for that by refering to the source given by 'thepancake', did some modification and wrote the code in VHDL.  

 

So I test the blocks with single type of symbols first, meaning all the 64 symbols are 0000 or 0001 or 0010 and so on until 1111. I find that the final output that I get is the same with the input to the IFFT block. However, when I tried mixing several symbols together in the 64-length, then the results becomes different, it is not the same as the my input to the IFFT block.  

 

I attached my project files, in that project the 64-length input is 1111,1111,1111,1111,0000,1111,...,1111 (total 64 symbols). The output is completely different from what I expected. Suppose the output should be 32 + j32, 32 + j32, 32 + j32, 32 + j32, -96 - j96, 32 + j32, ... ,32 + j32. But the output turns out to be 32 + j32, 32 + j32, 32 + j32, 32 + j32, -144 - j144, 32 + j32,..., 48 + j48, 32 + j32, ..., 64 + j64,32 + j32,... ,32 + j32. Need to run the project to see total waveform. 

 

I used functional simulation mode. The device is Cyclone II. Quartus 8.1 web edition. I wonder what caused the output to be like that.:confused:
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Altera_Forum
Honored Contributor II
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Just answered the same question... see the other thread....

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Altera_Forum
Honored Contributor II
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Right after reset_n is asserted, sink_ready isn't asserted yet... if I recall correctly, it stays de-asserted for one cycle (can be more, I don't remember).... essentially, you are sending data to the core before the core is ready to accept more data.... hence you are getting the 11 error.... and this is also why sink_ready de-asserts as well...

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Altera_Forum
Honored Contributor II
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hi bellman,I met the same problem as you said, if I mixed the real and imaginary data I find that the outputs change, if you finish this project, I'd like to see and thank you

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