Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,051 Views

FFT Mega Core IP

I am working on FFT MegaCore IP. I would like to give 64 points to the generated file and get the output using Altera DE2 board not the simulation. 

 

I built a top level file.v to pass the inputs to the generated fft file. This top level file looks like the test bench which is generated using the IP toolbench. Of course, there is no reading or writing from a file. The inputs comes from the code and the outputs should be displayed using LEDR on the board. 

 

I hope someone can help me, please.
0 Kudos
9 Replies
Altera_Forum
Honored Contributor I
90 Views

so the problem is getting the data in and out of the FFT on the DE2 from your PC?

Altera_Forum
Honored Contributor I
90 Views

No. 

The problem is how to pass inputs and get the outputs using the Altera FPGA board. There is no relation with the PC at all. 

 

There are the data: 

assign inputdata [1] = 15; 

assign inputdata [2] = 1; 

assign inputdata [3] = 5; 

assign inputdata [4] = 10; 

assign inputdata [5] = 5; 

assign inputdata [6] = 1; 

assign inputdata [7] = 6; 

assign inputdata [8] = 7; 

assign inputdata [9] = 5;  

assign inputdata [10] = 11;  

assign inputdata [11] = 5;  

assign inputdata [12] = 10;  

assign inputdata [13] = 5;  

assign inputdata [14] = 1;  

assign inputdata [15] = 10;  

assign inputdata [16] = 5;  

assign inputdata [17] = 6; 

assign inputdata [18] = 2; 

assign inputdata [19] = 3; 

assign inputdata [20] = 8; 

assign inputdata [21] = 9; 

assign inputdata [22] = 1; 

assign inputdata [23] = 5; 

assign inputdata [24] = 10; 

assign inputdata [25] = 5; 

assign inputdata [26] = 1; 

assign inputdata [27] = 9; 

assign inputdata [28] = 8; 

assign inputdata [29] = 2;  

assign inputdata [30] = 6;  

assign inputdata [31] = 5;  

assign inputdata [32] = 10;  

assign inputdata [33] = 5;  

assign inputdata [34] = 8;  

assign inputdata [35] = 4;  

assign inputdata [36] = 9;  

assign inputdata [37] = 2; 

assign inputdata [38] = 4; 

assign inputdata [39] = 5; 

assign inputdata [40] = 9; 

assign inputdata [41] = 7; 

assign inputdata [42] = 9; 

assign inputdata [43] = 5; 

assign inputdata [44] = 10; 

assign inputdata [45] = 5; 

assign inputdata [46] = 1; 

assign inputdata [47] = 15; 

assign inputdata [48] = 20; 

assign inputdata [49] = 5;  

assign inputdata [50] = 25;  

assign inputdata [51] = 23;  

assign inputdata [52] = 10;  

assign inputdata [53] = 5;  

assign inputdata [54] = 15;  

assign inputdata [55] = 15;  

assign inputdata [56] = 11;  

assign inputdata [57] = 1; 

assign inputdata [58] = 7; 

assign inputdata [59] = 17; 

assign inputdata [60] = 19; 

assign inputdata [61] = 5; 

assign inputdata [62] = 1; 

assign inputdata [63] = 5; 

assign inputdata [64] = 10; 

 

 

 

These data are passed to the generated file but there is no output from the FFT generated file.
Altera_Forum
Honored Contributor I
90 Views

i am still not quite sure what you are doing, maybe posting a block diagram would help? how will you verify the output data from the FFT? 

 

sounds like you are feeding the FFT 64 samples from a lookup table, hopefully into the sink_real and sink_imag inputs of the FFT? you could try using SignalTap on the source_real and source_imag outputs of the FFT. 

 

other than that have you verified functionality in simulation? the Avalon Streaming signals can take a little bit of work to get right.
Altera_Forum
Honored Contributor I
90 Views

I test the output from the FFT using the LED on the FPGA board. 

 

Unfortunately, the LED are always off == there is no outputs. 

 

I am also test the outputs using a logic analyzer. Also, the outputs are always zeros.  

 

I will attach the top level file here. If you do not mind please browse it and tell me what is wrong, please.
Altera_Forum
Honored Contributor I
90 Views

Hi Mr. thepancake, 

 

I hope you can help me. 

 

Now, I get some output but the sink_ready is always zero. 

 

Can you help me to figure it out?
Altera_Forum
Honored Contributor I
90 Views

hello, 

 

i'm a bit busy at work lately and Verilog is not my native tongue. :) 

 

source_ready and sink_valid look like they should be correct. is there anything on the source_error outputs? 

 

do you have ModelSim waveforms?
Altera_Forum
Honored Contributor I
90 Views

No, there is no source_errors. 

 

I got a single output. I mean only one point as an output. I should have 64 points as output. 

And the sink_ready is always 0. 

 

I used this code attached here. I am using the logic analyzer but I will try to use the modelsim.
Altera_Forum
Honored Contributor I
90 Views

Check the attachment. i m using a ROM to provide inputs to controller. controller genrates proper SOP, EOP and Valid signals and passes them to FFT IP Core. the results of the IP Core are the also used as output of the controller. the symbol file attached will explain it all 

 

Regards.
SYadl2
Beginner
82 Views

Hi,

we are facing issues with out put signals from FFT in board testing. But everything working fine in simulation.

 

is your issue is solved??