Right now I am trying to read 16 bit values from memory and put the data into the FFT Megacore function I have in my design. The only problem is that in my Verilog project, the sink_ready value never goes to 1 and therefore I can never push data into it. I have a VHDL implementation where I am reading from memory as well and it works as desired. This is acquiring data through the line in however.In the Verilog implementation I have attached the ADDA GPIO card to my DE1 board. In SignalTap I am reading from the ADDA card just fine, writing those values to memory just fine, and can read those same values from memory just fine as well. The only issue so far is that the FFT sink_ready value never goes to 1 so I can never push data through it. I have already tried scouring the forum here but only found older posts or problems that weren't relevant to the sink_ready value. I was wondering if anyone would hopefully know anything that would get in the way of the FFT Megacore outputting a 1 for the sink_ready. I have tried rereading the FFT Megacore manual many times too but can't seem to locate anything (though, it is also very long and it is possible I missed something while reading through trying to resolve this tedious issue).
Alright I was able to dig a bit deeper into the forums and discovered that if you assert reset-n, then sink_ready generates a signal of '1' afterward. I was under the impression that reset-n was to be asserted only after the use and not prior. I'm still trying to figure out how to pass data into the FFT but seeing sink_ready finally go to 1 is a good first step and I hope someone experiencing the same issue can quickly read this instead of having to dig deep as I did.
Hello,I am facing a similar problem with the FFT IP core, however, my issue is different in that sink_ready does not always remain 0, but becomes don't care (StX). I have looked at similar posts, and some of those problem (including the one in this thread) seemed to have been because of the reset_n input. I assert (set to 0) this signal and keep it asserted for many clock cycles (about 100), and sink_ready is 0 during this time. One cycle after I de-assert reset_n (set to 1), sink_ready becomes X. I also tried making this de-assertion happen at both the falling and the rising edge of the clock, but neither way worked. I am using variable streaming mode, with fixed-point data representation. I thought the problem could be that I set the input values before the core is ready, so I assigned don't cares to input real and imaginary parts to avoid this. I have also looked at the example design for this core generated by QSYS, and have not been able to find what I am doing wrong. I would appreciate it if anyone could let me know if they have seen this problem before and/or know how to solve it.
Hi Behrazv,Yes, this is important to issue an reset to the IP at the beginning of the simulation or when you power up the device. If the sink_ready signal becomes don't care (Stx) in simulation, it could be due to certain library files was missing. Assuming you are using Model-sim to run the simulation, you may refer to the simulation script "msim_setup.tcl" that generated by the IP for all of the necessary simulation files. Best Regards, Terence (This message was posted on behalf of Intel Corporation)