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BP_S
Beginner
532 Views

FFT block is not working when the hard floating point blocks are enabled?

The FFT IP is not correctly behaving when the hard floating point blocks are enabled for arria 10 device.

When the option is disabled in the parameter editor the FFT block is working fine.

 

The FFT is configured for variable streaming , single precision floating point, 2048 point forward FFT,input and output order are natural.

 

I am giving a single 2048 time domain sample packet as input. The expected output should be 2048 samples in a single packet, which is not observed when hard floating point blocks are enabled.

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3 Replies
CheePin_C_Intel
Employee
49 Views

Hi, As I understand it, you have some inquiries related to the FFT block behavior. To ensure we are on the same page, just would like to check with you on the following: 1. Mind further elaborate on the specific incorrect behavior that you are referring to? ie missing sample, missing SOP/EOP, corrupted output data and etc. Some screenshots will be helpful. 2. What is the Quartus version that you are using? 3. Sorry for any confusion, would you mind to further elaborate on the "hard floating point blocks" that you are referring to? Is it a parameter of the A10 FFT IP? 4. Mind share with me your .qsys of the FFT IP so that I can have a better understanding of your configuration. 5. Just would like to check with you if you are observing the issue in hardware or simulation? If it is hardware, would you mind to help performing a Modelsim simulation just to isolate any potential functional issue prior to hardware test. 6. If you observe similar issue with Modelsim simulation, mind share with me your simulation design together with steps to run and replicate the observation? This will be helpful for further debugging on my side. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
BP_S
Beginner
49 Views

Hi Chee Pin,

There are the answers to your queries

 

1) I am giving a single 2048 packet as input, a single 2048 packet output is expected. But the output has multiple sop and eop , the valid signal never goes down. The output data is also incorrect. Find the below screeshots

 

The input data i am givoingfft_input.PNG

The output i am getting

fft_out.PNG

fft_out2.PNG

 

2) Quartus Prime pro 17.1.0

 

3) It is in the ip parameter editor guihard_float.PNG

4) qsys is attached as a zip file

 

5) I am seeing this issue in hardware using signal tap.

 

 

CheePin_C_Intel
Employee
49 Views

Hi, Thanks for sharing the files and screenshots. Sorry as the screenshots are not very clear but I have tried my best to read the SOP/EOP signaling. As I understand it from screenshot #2, there are output data but seems like there are two SOPs. As for screenshot #3, there are two SOP or two EOPs within the same output packet. To further narrow down the issue, would you mind to perform a Modelsim simulation with the same FFT configuration as well as same data output? This will be helpful to have a golden comparison. Also, it can help to isolate any functional behavior prior to hardware testing. By the way, would you mind to attach a zip of the signaltap screenshots so that I can have a clearer view? Sorry for the inconvenience. Also, it would be great if you could further elaborate on the incorrect output data that you are referring to? Is it that you are comparing with a golden output but they are not matching? Thank you.
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