I've been posting questions regarding design hiccups I've been encountering in my project. Thanks to those who responded in the past.I'm doing a phase correlation calculation in the fpga between an image and a shifted version of the image to determine the relative spatial shift between the two. This is an image registration operation. Basically, I take the 2D fft of each image. Normalize their values to themselves to get a complex value with magnitude = 1. The phase angle info is what I am interested in. I then do a complex conjugate multiply of the two 2D ffts so that the result is magnitude 1.0 at angle (phi1 - phi2). This result is fed thru a 2D ifft to get back to spatial domain and the location of the peak is the amount of shift between the two original images. One of my major issues is the fft value going to zero in the fpga core d/t limited resolution of integer arithmetic. This causes divide by zero issues in the normalization step. I can watch for zeros in the verilog stream but have no idea what to substitute for them without corrupting phase information which is critical to this algorithm. Has anybody out there implemented this algorithm in an fpga and, if so, how does one get around this issue. I'm about ready to pull out the few remaining hairs I have on my head. Thanks for any input/ideas you may have.
I had the same problems when doing an algorithm for logs. Not sure on the number of bits you are using. But what I did was use say 4 bits out of 16 as a fractional decimal. Instead of allowing the value to zero, let it go to the smallest fractional part (1/16). This keeps the answer close to zero, so the results are about right.I also would recommend simulating the math in software. This way you can try different values for zero, and find an optimum number for your needs.