FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

FFT implemented within MAX 10 FPGA

torquay_mark
Beginner
223 Views

Does anyone have experience of FFTs within the MAX10 family? I note that these devices do not feature DSP blocks but do contain 18X18 multipliers. Are multipliers, LEs and RAM all that this IP requires for implementation?

 

I have created a qsys FFT block to my requirements in a project targeting the MAX 10 and generating the block gave no errors but I assume the resources are only checked at compile time?

 

Thanks

Mark

0 Kudos
1 Reply
CheePin_C_Intel
Employee
118 Views

Hi Mark,

 

As I understand it, you have some inquiries related to the FFT IP support in Max 10 devices. For your information, as I refer to the FFT IP Core User Guide -> "DSP IP Core Device Family Support", the Max 10 is supported for FFT IP. Therefore, there should be no issue for you to instantiate the IP in the device.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

Reply