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Altera_Forum
Honored Contributor I
751 Views

FFT output scaling

I will be grateful if anyone can help me here, because I'm having a really hard time trying to sort things out. 

 

I've already made a VHDL test bench to simulate a transform of a sinusoidal signal, but, I can't check if the result is correct, cause I'm not sure about the scaling procedure. The FFT Megacore user guide says I need to: 

 

[LIST]Determine the length of the full scale register, according to the given table - DONE[/LIST] 

[LIST]Map the output data to the appropriate location within the register, according to the exponent value - DONE[/LIST] 

[LIST]Sign extend the data within the full scale register.[/LIST] 

 

I'm stuck in the last item, because I don't know how to do that. The guide shows the following example: 

 

case (exp) 

6'b110101 : //-11 Set data equal to MSBs 

begin 

full_range_real_out[26:0] <= {real_in[15:0],11'b0}; 

full_range_imag_out[26:0] <= {imag_in[15:0],11'b0}; 

end 

6'b110110 : //-10 Equals left shift by 10 with sign extension 

begin 

full_range_real_out[26] <= {real_in[15]}; 

full_range_real_out[25:0] <= {real_in[15:0],10'b0}; 

full_range_imag_out[26] <= {imag_in[15]}; 

full_range_imag_out[25:0] <= {imag_in[15:0],10'b0}; 

end 

6'b110111 : //-9 Equals left shift by 9 with sign extension 

begin 

full_range_real_out[26:25] <= {real_in[15],real_in[15]}; 

full_range_real_out[24:0] <= {real_in[15:0],9'b0}; 

full_range_imag_out[26:25] <= {imag_in[15],imag_in[15]}; 

full_range_imag_out[24:0] <= {imag_in[15:0],9'b0}; 

end 

endcase 

 

I have no idea why, in the last case for example, the real_in[15] was assigned to full_range_real_out[26:25]. I thought I was supposed to left shift by 9 and fill the remaining bits with zeroes. Can somebody explain what is going on?
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7 Replies
Altera_Forum
Honored Contributor I
48 Views

I am not familiar with your fft scaling but here is explanation of your statements. 

 

 

--- Quote Start ---  

 

full_range_real_out[26:25] <= {real_in[15],real_in[15]}; 

 

--- Quote End ---  

this is sign bit repeated twice to sign extend the value 

 

 

--- Quote Start ---  

 

full_range_real_out[24:0] <= {real_in[15:0],9'b0}; 

 

--- Quote End ---  

this is left shift by inserting 9 zeros on new LSBs. the original bits 15:0 are in effect multiplied by 2^9 

 

since 9 zero LSBs, then 15:0 make 25 bits while full range is 27 bits then sign bit is repeated twice.
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

 

since 9 zero LSBs, then 15:0 and one sign bit make 26 bits while full range is 27 bits then sign bit repeated. 

--- Quote End ---  

 

 

So I must repeat the sign bit as many times as needed to match the full range width? For example, assume I would like to left shift by 5, so I do: 

 

full_range_real_out [26:21] <= {real_in[15],real_in[15],real_in[15],real_in[15],real_in[15],real_in[15]}; 

 

full_range_real_out [20:0] <= {real_in [15:0],5'b0};
Altera_Forum
Honored Contributor I
48 Views

correct. 

In 2's complement. a number is same value if you sign extend the MSBs. 

In unsigned system you only sign extend with zeros.
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

correct. 

In 2's complement. a number is same value if you sign extend the MSBs. 

In unsigned system you only sign extend with zeros. 

--- Quote End ---  

 

 

Now that you mentioned, I'm not sure if the input format is in 2's complement as well. The user guide is not clear about it, but I assume it is indeed 2's complement.
Altera_Forum
Honored Contributor I
48 Views

i think all of the fixed point DSP IP uses 2's complement

Altera_Forum
Honored Contributor I
48 Views

Here is another question. What's the use of bit reverse order and -N/2 to N/2 order? Isn't it more intuitive to work with natural order? What's the order used by the streaming, burst and buffered burst data flow?

Altera_Forum
Honored Contributor I
48 Views

its more intuitive to work with natural order, but it uses quite a bit more RAM. depending on your application, you might develop in natural order but change to bit reversed order to save resources in the final design

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