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Altera_Forum

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05-24-2011
05:27 PM

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FFT output scaling

I will be grateful if anyone can help me here, because I'm having a really hard time trying to sort things out.

I've already made a VHDL test bench to simulate a transform of a sinusoidal signal, but, I can't check if the result is correct, cause I'm not sure about the scaling procedure. The FFT Megacore user guide says I need to: [LIST]Determine the length of the full scale register, according to the given table - DONE[/LIST] [LIST]Map the output data to the appropriate location within the register, according to the exponent value - DONE[/LIST] [LIST]Sign extend the data within the full scale register.[/LIST] I'm stuck in the last item, because I don't know how to do that. The guide shows the following example: case (exp) 6'b110101 : //-11 Set data equal to MSBs begin full_range_real_out[26:0] <= {real_in[15:0],11'b0}; full_range_imag_out[26:0] <= {imag_in[15:0],11'b0}; end 6'b110110 : //-10 Equals left shift by 10 with sign extension begin full_range_real_out[26] <= {real_in[15]}; full_range_real_out[25:0] <= {real_in[15:0],10'b0}; full_range_imag_out[26] <= {imag_in[15]}; full_range_imag_out[25:0] <= {imag_in[15:0],10'b0}; end 6'b110111 : //-9 Equals left shift by 9 with sign extension begin full_range_real_out[26:25] <= {real_in[15],real_in[15]}; full_range_real_out[24:0] <= {real_in[15:0],9'b0}; full_range_imag_out[26:25] <= {imag_in[15],imag_in[15]}; full_range_imag_out[24:0] <= {imag_in[15:0],9'b0}; end . . . endcase I have no idea why, in the last case for example, the real_in[15] was assigned to full_range_real_out[26:25]. I thought I was supposed to left shift by 9 and fill the remaining bits with zeroes. Can somebody explain what is going on?Link Copied

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Altera_Forum

Honored Contributor I

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05-24-2011
05:55 PM

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I am not familiar with your fft scaling but here is explanation of your statements.

--- Quote Start --- full_range_real_out[26:25] <= {real_in[15],real_in[15]}; --- Quote End --- this is sign bit repeated twice to sign extend the value --- Quote Start --- full_range_real_out[24:0] <= {real_in[15:0],9'b0}; --- Quote End --- this is left shift by inserting 9 zeros on new LSBs. the original bits 15:0 are in effect multiplied by 2^9 since 9 zero LSBs, then 15:0 make 25 bits while full range is 27 bits then sign bit is repeated twice.
Altera_Forum

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05-24-2011
06:14 PM

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Altera_Forum

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05-24-2011
06:17 PM

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correct.

In 2's complement. a number is same value if you sign extend the MSBs. In unsigned system you only sign extend with zeros.
Altera_Forum

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05-24-2011
06:31 PM

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Altera_Forum

Honored Contributor I

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05-24-2011
06:42 PM

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i think all of the fixed point DSP IP uses 2's complement

Altera_Forum

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05-25-2011
12:40 PM

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Altera_Forum

Honored Contributor I

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05-25-2011
03:35 PM

48 Views

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